Datasheet

ADS850
SBAS154C
13
www.ti.com
CLOCK INPUT REQUIREMENTS
Clock jitter is critical to the SNR performance of high-speed,
high-resolution ADCs. It leads to aperture jitter (t
A
) which
adds noise to the signal being converted. The ADS850
samples the input signal on the rising edge of the CLK input.
Therefore, this edge should have the lowest possible jitter.
The jitter noise contribution to total SNR is given by the
following equation. If this value is near your system require-
ments, input clock jitter must be reduced.
JitterSNR
t
rmssignaltormsnoise
IN A
=
ƒ
20
1
2
log
π
Where: ƒ
IN
is Input Signal Frequency
t
A
is rms Clock Jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
a 50% duty cycle (t
H
= t
L
), along with fast rise and fall times
of 2ns or less.
DIGITAL OUTPUTS
The digital outputs of the ADS850 are designed to be
compatible with both high speed TTL and CMOS logic
families. The driver stage for the digital outputs is supplied
through a separate supply pin, VDRV, which is not con-
nected to the analog supply pins. By adjusting the voltage on
VDRV, the digital output levels will vary respectively. There-
fore, it is possible to operate the ADS850 on a +5V analog
supply while interfacing the digital outputs to 3V logic.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Larger capacitive loads
demand higher charging currents as the outputs are chang-
ing. Those high current surges can feed back to the analog
portion of the ADS850 and influence the performance. If
necessary, external buffers or latches may be used which
provide the added benefit of isolating the ADS850 from any
digital noise activities on the bus coupling back high fre-
quency noise. In addition, resistors in series with each data
line may help maintain the ac performance of the ADS850.
Their use depends on the capacitive loading seen by the
converter. Values in the range of 100Ω to 200Ω will limit the
instantaneous current the output stage has to provide for
recharging the parasitic capacitances, as the output levels
change from LOW to HIGH or HIGH to LOW.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multi-layer PC boards are recommended
for best performance since they offer distinct advantages like
minimizing ground impedance, separation of signal layers by
ground layers, etc. It is recommended that the analog and
digital ground pins of the ADS850 be joined together at the
IC and be connected only to the analog ground of the
system.
The ADS850 has analog and digital supply pins, however,
the converter should be treated as an analog component and
all supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise that would otherwise be
coupled into the converter and degrade the achievable per-
formance.
Because of the pipeline architecture, the converter also
generates high frequency current transients and noise that
are fed back into the supply and reference lines. This
requires that the supply and reference pins be sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the analog supplies. In most cases, 0.1µF ce-
ramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin. There-
fore, they should be located as close to the supply pins as
possible. In addition, a larger size bipolar capacitor (1µF to
22µF) should be placed on the PC board in close proximity
to the converter circuit.
FIGURE 9. Recommended Bypassing for Analog Supply Pins.
+V
S
1, 2
GND
ADS850
+
0.1µF 0.1µF
+V
S
36
GND
0.1µF
+V
S
3, 4
2.2µF
VDRV
26
0.1µF
+5V/+3V+5V
NOTE: All “GND” pins should be tied together.