Datasheet

External
DATACLK
.
2 3 4 3534 361716 20 21191
Null
D Q
A00
D Q
Null
D Q
B00
D Q
A15
D Q
A16
D Q
B15
D Q
B16
D Q
TAG(A)
TAG(B)
DATA (A)
DATA (B)
DATACLK
(both A & B)
SYNC
(both A & B)
(both A & B)
DATA ( B )
Nth Conversion Data
B15 A15B00
B13B14 B01 A00A14 A13 A01
DATA ( A )
A15 A00A13A14 A01
18
Null
A
Null
B
Null
A
ADS8509A
TAG
DATA
DATACLK
ADS8509B
TAG
DATA
DATACLK
Processor
SCLK
GPIO
GPIO
SDI
TAG(A) = 0
TAG(A) = 0
R/C
CS
R/C
CS
R/C
BUSY
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
ADS8509
SLAS324C –OCTOBER 2004–REVISED APRIL 2010 www.ti.com
Figure 27. Timing of TAG Feature With Single Conversion (Using External DATACLK)
ANALOG INPUTS
The ADS8509 has six analog input ranges as shown in Table 2. The offset and gain specifications are factory
calibrated with 0.1%, 0.25-W, external resistors as shown in Figure 29 and Figure 30. The external resistors can
be omitted if larger gain and offset errors are acceptable or if using software calibration. The hardware trim
circuitry shown in Figure 29 and Figure 30 can reduce the errors to zero.
The analog input pins R1
IN
, R2
IN
, and R3
IN
have ±25-V overvoltage protection. The input signal must be
referenced to AGND1. This minimizes the ground loop problem typical to analog designs. The analog input
should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
Figure 28.
The ADS8509 can operate with its internal 2.5-V reference or an external reference. An external reference
connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-kΩ resistor
that separates pin 6 from the internal reference (see the illustration on page 1). The load varies with the
difference between the internal and external reference voltages. The external reference voltage can vary from
2.3 V to 2.7 V. The internal reference is approximately 2.5 V. The reference, whether internal or external, is
buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8509 is factory tested with 2.2-mF capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor
should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A
smaller capacitor can be used but it may degrade SNR and SINAD. The capacitor on pin 5 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 mF
can cause the buffer to become unstable and may not hold sufficient charge for the CDAC. The parts are tested
to specifications with 2.2 mF so larger capacitors are not necessary. The equivalent series resistor (ESR) of these
compensation capacitors is also critical. The total ESR must be kept under 3 Ω. See the TYPICAL
CHARACTERISTICS section concerning how ESR affects performance.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4-kΩ resistor and affects gain.
The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference at the
CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar input
structure, the ADS8509 does not require a second high-speed amplifier used as a buffer to isolate the CAP pin
from the signal dependent current in the R3
IN
pin but can tolerate it if one does exist.
18 Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8509