Datasheet

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External
DATACLK
.
2 3 4 3130 321312 16 17151
Null
D Q
A00
D Q
Null
D Q
B00
D Q
A11
D Q
A12
D Q
B11
D Q
B12
D Q
TAG(A)
TAG(B)
DATA (A)
DATA (B)
DATACLK
(both A & B)
SYNC
(both A & B)
(both A & B)
DATA ( B )
Nth Conversion Data
B11 A11B00
B09B10 B01 A00A10 A09 A01
DATA ( A )
A11 A00A09A10 A01
14
Null
A
Null
B
Null
A
ADS8508A
TAG
DATA
DATACLK
ADS8508B
TAG
DATA
DATACLK
Processor
SCLK
GPIO
GPIO
SDI
TAG(A) = 0
TAG(A) = 0
R/C
CS
R/C
CS
R/C
BUSY
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
ANALOG INPUTS
ADS8508
SLAS433 – SEPTEMBER 2005
Figure 26. Timing of TAG Feature With Single Conversion (Using External DATACLK)
The ADS8508 has six analog input ranges as shown in Table 3 . The offset and gain specifications are factory
calibrated with 0.1%, ¼-W, external resistors as shown in Figure 28 and Figure 29 . The external resistors can be
omitted if larger gain and offset errors are acceptable or if using software calibration. The hardware trim circuitry
shown in Figure 28 and Figure 29 can reduce the errors to zero.
The analog input pins R1
IN
, R2
IN
, and R3
IN
have ±25-V overvoltage protection. The input signal must be
referenced to AGND1. This will minimized the ground loop problem typical to analog designs. The analog input
should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
Figure 27 .
The ADS8508 can operate with its internal 2.5-V reference or an external reference. An external reference
connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-k Ω resistor
that separates pin 6 from the internal reference (see the illustration on page 1). The load will vary with the
difference between the internal and external reference voltages. The external reference voltage can vary from
2.3 V to 2.7 V. The internal reference will be approximately 2.5 V. The reference, whether internal or external, is
buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8508 is factory tested with 2.2-µF capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor
should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A
smaller capacitor can be used but it may degrade SNR and SINAD The capacitor on pin 5 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 µF
can cause the buffer to become unstable may not hold sufficient charge for the CDAC. The parts are tested to
specifications with 2.2 µF so larger capacitors are not necessary. The ESR (equivalent series resistance) of
these compensation capacitors is also critical. Keep the total ESR under 3 Ω . See the TYPICAL CHARACTER-
ISTICS section for how the performance is affected by ESR.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4-k Ω resistor and will affect
gain. The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference
at the CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar
input structure, the ADS8508 does not require a second high speed amplifier used as buffer to isolate the CAP
pin from the signal dependent current in the R3
IN
pin but can tolerate it if one do exist.
18