Datasheet

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TAG FEATURE
ADS8508
SLAS433 – SEPTEMBER 2005
Whether reading during sampling or during conversion a SYNC pulse is generated whenever at least one rising
edge of the external clock occurs while the part is not in the read state. In the discontinuous external clock with
SYNC mode a SYNC pulse follows the first rising edge after the read command. The data is shifted out after the
SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can
be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the
falling edge and then on the next rising edge. Thus 13 clock pulses after the read command are required to read
on the falling edge, and 14 clock pulses are necessary to read on the rising edge.
Table 2. DATACLK Pulses
DATACLK PULSES REQUIRED
DESCRIPTION
WITH SYNC WITHOUT SYNC
Read on falling edge of DATACLK 13 12
Read on rising edge of DATACLK 14 13
If the clock is entirely inactive when not in the read state no SYNC pulse is generated. In this case the first rising
clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In this
discontinuous external clock mode with no SYNC, 12 clocks are necessary to read the data on the falling edge
and 13 clocks for reading on the rising edge. Data always represents the conversion already completed.
The TAG feature allows the data from multiple ADS8508 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 26 . The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the t
d11
constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 26 , that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 12 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 26 the NULL bit becomes a zero between each data
word.
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