Datasheet

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BASIC OPERATION
READING DATA
INTERNAL DATACLK
EXTERNAL DATACLK
ADS8508
SLAS433 – SEPTEMBER 2005
Two signals control conversion in the ADS8508: CS and R/ C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/ C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/ C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8508 will clock out data whenever
R/ C is brought high and the external clock is active. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/ C. The ADS8508 provides a TAG input for cascading multiple
converters together.
The conversion result is available as soon as BUSY returns to high therefore, data always represents the
conversion previously completed even when it is read during a conversion. The ADS8508 outputs serial data in
either straight binary or binary two’s compliment format. The SB/ BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up will not produce a valid conversion result.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/ INT pin
controls this function. If external clock is used the TAG input can be used to daisy-chain multiple ADS8508 data
pins together.
In the internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/ INT is low. 12 clock pulses are generated at the beginning of
each conversion after timing t
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is satisfied, i.e. you can only read previous conversion result during conversion.
DATACLK returns to low when it is inactive. The 12 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. DATA pin returns to the state of TAG pin
input sensed at the start of transmission.
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
When EXT/ INT is set high, the R/ C and CS signals control the read state. When the read state is initiated the
result from the previously completed conversion is shifted out the DATA pin synchronous to the external clock
that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum
external clock speed of 28.5 MHz allows data shifted out quickly either at the beginning of conversion or the
beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the
external clock run only while reading data. This is the discontinuous clock mode. Since the external clock is not
synchronized to the internal clock that controls conversion slight changes in the external clock can cause
conflicts that can corrupt the conversion process. Specifications with a continuously running external clock
cannot be guaranteed. It is especially important that the external clock does not run during the second half of the
conversion cycle (approximately the time period specified by t
d11
, see timing table).
In the discontinuous clock mode data can be read during conversion or during sampling, with or without a SYNC
pulse. Data read during a conversion must meet the t
d11
timing specification. Data read during sampling must be
complete before starting a conversion.
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