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BUSY
STATUS
(N+1) th Accquisition
Error
Correction
Nth Conversion
External
DATACLK
SDATA
Nth Conversion Data
D15
0 1 2 3
1514 16
TAG
T01
D05D10D12D13D14
T00 T04
T03T02
T13T12T11T06 T16T15T14
Tyy
54
11 12 1310
D11
T05
D04 D03 D02 D01
Txx
T00
D00
Null
T17
Null
R/C
EXT/INT tied high, CS tied low
t
w1
+ t
su1
starts READ
t
w1
t
d1
t
w2
t
su1
t
d3
t
d11
t
d2
t
conv
t
acq
t
d3
t
d1
t
su3
t
w3
t
c2
t
w4
t
su1
t
d8
t
d8
t
su3
t
h1
BUSY
STATUS
Error
Correction
Nth Conversion
External
DATACLK
SDATA
Nth Conversion Data
D15
0
1 2 3 1514 16
D05D10D12D13D14
54 11 12 1310
D11 D00D04 D03 D02 D01
R/C
EXT/INT tied high, CS and TAG tied low
Rising DATACLK change DATA, t
w1
+ t
su1
Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating t
d11
.
t
w1
t
d1
t
w2
t
d10
t
d3
t
su3
t
conv
t
d2
t
su1
t
w3
t
c2
t
w4
t
d11
t
d8
t
d8
TAG FEATURE
ADS8507
SLAS381 – DECEMBER 2006
Figure 38. Read After Conversion (Discontinuous External DATACLK)
Figure 39. Read During Conversion (Discontinuous External DATACLK)
The TAG feature allows the data from multiple ADS8507 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 40 . The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
19
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