Datasheet

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SERIAL OUTPUT
INTERNAL DATA CLOCK (During a Conversion)
EXTERNAL DATA CLOCK
EXTERNAL DATA CLOCK (After a Conversion)
EXTERNAL DATA CLOCK (During a Conversion)
ADS8507
SLAS381 – DECEMBER 2006
Table 5. Conversion and Data Timing, T
A
= -40 °C to 85 °C (continued)
t
21
R/ C to CS setup time 10 ns
t
22
Valid data after DATACLK high 25 ns
t
7
+ t
8
Throughput time 25 µs
Data can be clocked out with the internal data clock or an external data clock. When using serial output, be
careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins come out of Hi-Z state whenever
CS (pin 23) is low and R/ C (pin 22) is high. The serial output cannot be 3-stated and is always active. Refer to
the Applications Information section for specific serial interfaces. If external clock is used, the TAG input can be
used to daisy-chain multiple ADS8507 data pins together.
To use the internal data clock, tie EXT/ INT (pin 8) low. The combination of R/ C (pin 22) and CS (pin 23) low
initiates conversion N and activates the internal data clock (typically 900-kHz clock rate). The ADS8507 outputs
16 bits of valid data, MSB first, from conversion N–1 on SDATA (pin 19), synchronized to 16 clock pulses output
on DATACLK (pin 18). The data is valid on both the rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK remains low until the
next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the start of
transmission. Refer to Table 6 and Figure 36 .
To use an external data clock, tie EXT/ INT (pin 8) high. The external data clock is not and cannot be
synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the
output mode of the ADS8507, CS (pin 23) must be low and R/ C (pin 22) must be high. DATACLK must be high
for 20% to 70% of the total data clock period; the clock rate can be between DC and 10 MHz. Serial data from
conversion N can be output on SDATA (pin 19) after conversion N is completed or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/ C to initiate conversions.
While this is perfectly acceptable, there is a possible problem when using an external data clock. At an
indeterminate point from 12 µs after the start of conversion N until BUSY rises, the internal logic shifts the
results of conversion N into the output register. If CS is low, R/ C high, and the external clock is high at this point,
data is lost. So, with CS low, either R/ C and/or DATACLK must be low during this period to avoid losing valid
data.
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS
low and R/ C high, valid data from conversion N is output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the
external data clock. The LSB is valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin
20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 17th
falling edge and the 18th rising edge of DATACLK; the second input bit is valid on the 18th falling edge and the
19th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table 6 and Figure 38 .
After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs after
the start of conversion N. Do not attempt to clock out data from 12 µs after the start of conversion N until BUSY
(pin 24) rises; this results in data loss. NOTE: For the best possible performance when using an external data
clock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clock
can cause digital feedthrough degrading the converter's performance. Refer to Table 6 and Figure 39 .
16
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