Datasheet

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t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
9
t
21
t
9
Hi-Z State High Byte Hi-Z State Low Byte Hi-Z State
t
4
t
3
t
1
R/C
BUSY
CS
Data Bus
BYTE
PARALLEL OUTPUT (During a Conversion)
ADS8507
SLAS381 – DECEMBER 2006
Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs
After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs after
the start of conversion N. Do not attempt to read data beyond 12 µs after the start of conversion N until BUSY
(pin 24) goes high; this may result in reading invalid data. Refer to Table 5 and Figure 33 and Figure 34 for
timing constraints.
Table 5. Conversion and Data Timing, T
A
= -40 °C to 85 °C
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert pulse width 0.04 12 µs
t
2
Data valid delay after R/ C low 18 20 µs
t
3
BUSY delay from start of conversion 85 ns
t
4
BUSY Low 19 20 µs
t
5
BUSY delay after end of conversion 90 ns
t
6
Aperture delay 40 ns
t
7
Conversion time 19 20 µs
t
8
Acquisition time 5 ns
t
9
Bus relinquish time 10 83 ns
t
10
BUSY delay after data valid 20 60 ns
t
11
Previous data valid after start of conversion 12 18 µs
t
12
Bus access time and BYTE delay 83 ns
t
13
Start of conversion to DATACLK delay 1.4 µs
t
14
DATACLK period 1.1 µs
t
15
Data valid to DATACLK high delay 20 75 ns
t
16
Data valid after DATACLK low delay 400 600 ns
t
17
External DATACLK period 100 ns
t
18
External DATACLK low 40 ns
t
19
External DATACLK high 50 ns
t
20
CS and R/ C to external DATACLK setup time 25 ns
15
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