Datasheet

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PARALLEL OUTPUT
PARALLEL OUTPUT (After a Conversion)
R/C
BUSY
MODE
Parallel
Data Bus
BYTE
t
1
t
3
t
4
t
1
t
3
t
6
t
7
t
5
t
6
t
8
t
12
t
11
t
10
t
12
t
2
t
9
t
12
t
12
t
12
t
9
t
12
Previous
High Byte Valid
Hi-Z
Previous High
Byte Valid
Previous Low
Byte Valid
Not Valid
High Byte
Valid
Low Byte
Valid
Hi-Z
High Byte
Valid
Acquire Convert Acquire Convert
ADS8507
SLAS381 – DECEMBER 2006
To use the parallel output, tie EXT/ INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left
unconnected. The parallel output is active when R/ C (pin 22) is high and CS (pin 23) is low. Any other
combination of CS and R/ C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on
D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the 8 most significant bits will be valid with the MSB
on D7. When BYTE is high, the 8 least significant bits are valid with the LSB on D0. BYTE can be toggled to
read both bytes within one conversion cycle.
Upon initial power up, the parallel output contains indeterminate data.
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N is available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
data. Refer to Table 5 and Figure 33 and Figure 34 for timing specifications.
Figure 33. Conversion Timing With Parallel Output ( CS and DATACLK Tied Low, EXT/INT Tied High)
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