Datasheet

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READING DATA
ADS8507
SLAS381 – DECEMBER 2006
CS and R/ C are internally ORed and level triggered. It is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/ C initiates conversion N, be sure the less critical
input is low at least t
su2
≥ 10 ns prior to the initiating input. If EXT/ INT (pin 8) is low when initiating conversion N,
serial data from conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal
Data Clock in the Reading Data section.
To reduce the number of control pins, CS can be tied low using R/ C to control the read and convert modes. This
has no effect when using the internal data clock in the serial output mode. The parallel output and the serial
output (only when using an external data clock), however, is affected whenever R/ C goes high and the external
clock is active. Refer to the Reading Data section. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/ C. The conversion result is available as soon as BUSY returns to
high therefore, data always represents the conversion previously completed even when it is read during a
conversion.
The ADS8507 outputs serial or parallel data in straight binary (SB) or binary 2's complement data output format.
If SB/ BTC (pin 7) is high, the output is in SB format, and if low, the output is in BTC format. Refer to Table 4 for
ideal output codes. The first conversion immediately following a power-up does not produce a valid conversion
result.
The parallel output can be read without affecting the internal output registers; however, reading the data through
the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on
the parallel port prior to reading the same data on the serial port, but data cannot be read through the serial port
prior to reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output
(1)
CS R/ C BUSY EXT/ INT DATACLK OPERATION
↓ 0 1 0 Output Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
0 ↓ 1 0 Output Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
↓ 0 1 1 Input Initiates conversion N. Internal clock still runs conversion process.
0 ↓ 1 1 Initiates conversion N. Internal clock still runs conversion process.
↓ 1 1 1 Input Conversion N completed. Valid data from conversion N clocked out on SDATA
synchronized to external data clock.
↓ 1 0 1 Input Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0 ↑ 0 1 Input Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0 0 ↑ X Input New conversion initiated without acquisition of a new signal. Data will be invalid. CS
and/or R/ C must be HIGH when BUSY goes HIGH.
X X 0 X X New convert commands ignored. Conversion N in progress..
(1) See Figure 37 , Figure 38 , and Figure 39 for constraints on data valid from conversion N–1.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION ANALOG INPUT BINARY 2's COMPLEMENT
STRAIGHT BINARY (SB/ BTC HIGH)
(SB/ BTC LOW)
Full-scale range ±10 0 V to 5 V 0 V to 4 V HEX
BINARY CODE BINARY CODE HEX CODE
CODE
Least significant bit (LSB) 305 µV 76 µV 61 µV
+Full-Scale (FS - 1LSB) 9.999695 V 4.999924 V 3.999939 V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF
Midscale 0 V 2.5 V 2 V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000
One LSB Below Midscale 305 µV 2.499924 V 1.999939 V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF
-Full-Scale -10 V 0 V 0 V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000
13
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