Datasheet

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External
DATACLK
.
2 3 4 2726 281312 16 17151
Null
D Q
A00
D Q
Null
D Q
B00
D Q
A11
D Q
A12
D Q
B11
D Q
B12
D Q
TAG(A)
TAG(B)
SDATA
(A)
SDATA (B)
DATACLK
(both A & B)
(both A & B)
SDATA
( B )
Nth Conversion Data
B11 A11B00
B9B10 B01 A00A10 A9 A01
SDATA ( A )
A11 A00A9A10 A01
14
Null
A
Null
B
Null
A
ADS8506A
TAG
DATA
DATACLK
ADS8506B
TAG
DATA
DATACLK
Processor
SCLK
GPIO
GPIO
SDI
TAG(A) = 0
TAG(A) = 0
R/C
CS
R/C
CS
R/C
BUSY
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
Nth Conversion
INPUT RANGES
ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the t
d11
constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 40 , that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 12 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 40 the NULL bit becomes a zero between each data
word.
Figure 40. Timing of TAG Feature With Single Conversion (Using External DATACLK)
The ADS8506 offers three input ranges: standard ± 10-V and 0-V to 5-V ranges, and a 0-V to 4-V range for
complete, single-supply systems. See Figure 42 and Figure 43 for the necessary circuit connections for
implementing each input range and optional offset and gain adjust circuitry. Offset and full-scale error
specifications are tested with the fixed resistors, see Figure 43 (full-scale error includes offset and gain errors
measured at both +FS and -FS). Adjustments for offset and gain are described in the Calibration section of this
data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
The input impedance, summarized in Table 1 , results from the combination of the internal resistor network (see
the front page of this product data sheet) and the external resistors used for each input range (see Figure 44 ).
The input resistor divider network provides inherent over-voltage protection to at least ± 5.5 V for R2
IN
and ± 12 V
for R1
IN
.
Analog inputs above or below the expected range yields either positive full-scale or negative full-scale digital
outputs, respectively. Wrapping or folding over for analog inputs outside the nominal range does not occur.
20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS8506