Datasheet

www.ti.com
1 2
t
su1
t
su1
CS
R/C
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
t
su1
t
su1
R/C
CS
External
DATACLK
R/C Set Low, Discontinuous Ext DATACLK
t
su2
t
su2
CS
R/C
t
su3
BUSY
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
t
d9
ADS8506
SLAS484B SEPTEMBER 2007 REVISED DECEMBER 2007
Table 6. Serial Timing Requirements, T
A
= 40 ° C to 85 ° C
PARAMETER MIN TYP MAX UNIT
t
w1
Pulse duration, convert 0.04 12 µ s
t
d1
Delay time, BUSY from R/ C low 12 20 ns
t
w2
Pulse duration, BUSY low 13.5 15 µ s
t
d2
Delay time, BUSY, after end of conversion 5 ns
t
d3
Delay time, aperture 5 ns
t
conv
Conversion time 13.5 15 µ s
t
acq
Acquisition time 10 11.5 µ s
t
conv
+ t
acq
Cycle time 25 µ s
t
d4
Delay time, R/ C low to internal DATACLK output 204 ns
t
c1
Cycle time, internal DATACLK 600 820 850 ns
t
d5
Delay time, data valid to internal DATACLK high 150 204 ns
t
d6
Delay time, data valid after internal DATACLK low 150 208 ns
t
c2
Cycle time, external DATACLK 35 ns
t
w3
Pulse duration, external DATACLK high 15 ns
t
w4
Pulse duration, external DATACLK low 15 ns
t
su1
Setup time, R/ C rise/fall to external DATACLK high 15 ns
t
su2
Setup time, R/ C transition to CS transition 10 ns
t
d8
Delay time, data valid from external DATCLK high 2 20 ns
t
d9
Delay time, CS rising edge to external DATACLK rising edge 10 ns
t
d10
Delay time, previous data available after CS, R/ C low 12 µ s
t
su4
Setup time, BUSY transition to first external DATACLK 5 ns
t
d11
Delay time, final external DATACLK to BUSY rising edge 2 µ s
t
su3
Setup time, TAG valid to rising DATACLK 0 ns
t
h1
Hold time, TAG valid after rising edge of DATACLK 2 ns
Figure 35. Critical Timing
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS8506