Datasheet

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EXTERNAL DATA CLOCK (After a Conversion)
EXTERNAL DATA CLOCK (During a Conversion)
ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS
low and R/ C high, valid data from conversion N is output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the
external data clock. The LSB is valid on the 12th falling edge and 13th rising edge of the data clock. TAG (pin
20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 13th
falling edge and the 14th rising edge of DATACLK; the second input bit is valid on the 14th falling edge and the
15th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table 6 and Figure 38 .
After conversion N has been initiated, valid data from conversion N – 1 can be read and is valid up to 12 µ s after
the start of conversion N. Do not attempt to clock out data from 12 µ s after the start of conversion N until BUSY
(pin 24) rises; this results in data loss. NOTE: For the best possible performance when using an external data
clock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clock
can cause digital feedthrough degrading the converter's performance. Refer to Table 6 and Figure 39 .
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