Datasheet

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PARALLEL OUTPUT (During a Conversion)
SERIAL OUTPUT
INTERNAL DATA CLOCK (During a Conversion)
EXTERNAL DATA CLOCK
ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
After conversion N has been initiated, valid data from conversion N – 1 can be read and is valid up to 12 µ s after
the start of conversion N. Do not attempt to read data beyond 12 µ s after the start of conversion N until BUSY
(pin 24) goes high; this may result in reading invalid data. Refer to Table 5 and Figure 33 and Figure 34 for
timing constraints.
Table 5. Parallel Conversion and Data Timing, T
A
= -40 ° C to 85 ° C
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert pulse width 0.04 12 µ s
t
2
Data valid delay after R/ C low 13.5 15 µ s
t
3
BUSY delay from start of conversion 85 ns
t
4
BUSY Low 13.5 15 µ s
t
5
BUSY delay after end of conversion 90 ns
t
6
Aperture delay 40 ns
t
7
Conversion time 13.5 15 µ s
t
8
Acquisition time 11.5 µ s
t
9
Bus relinquish time 10 83 ns
t
10
BUSY delay after data valid 20 60 ns
t
11
Previous data valid after start of conversion 13.5 15 µ s
t
12
Bus access time and BYTE delay 10 83 ns
t
21
R/ C to CS setup time 10 ns
t
7
+ t
8
Throughput time 25 µ s
Data can be clocked out with the internal data clock or an external data clock. When using serial output, be
careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins come out of Hi-Z state whenever CS
(pin 23) is low and R/ C (pin 22) is high. The serial output cannot be 3-stated and is always active. Refer to the
Applications Information section for specific serial interfaces. If external clock is used, the TAG input can be used
to daisy-chain multiple ADS8506 data pins together.
To use the internal data clock, tie EXT/ INT (pin 8) low. The combination of R/ C (pin 22) and CS (pin 23) low
initiates conversion N and activates the internal data clock (typically 900-kHz clock rate). The ADS8506 outputs
12 bits of valid data, MSB first, from conversion N – 1 on SDATA (pin 19), synchronized to 12 clock pulses output
on DATACLK (pin 18). The data is valid on both the rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After the 12th clock pulse, DATACLK remains low until the
next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the start of
transmission. Refer to Table 6 and Figure 36 .
To use an external data clock, tie EXT/ INT (pin 8) high. The external data clock is not and cannot be
synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the
output mode of the ADS8506, CS (pin 23) must be low and R/ C (pin 22) must be high. DATACLK must be high
for 20% to 70% of the total data clock period; the clock rate can be between DC and 10 MHz. Serial data from
conversion N can be output on SDATA (pin 19) after conversion N is completed or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/ C to initiate conversions.
While this is perfectly acceptable, there is a possible problem when using an external data clock. At an
indeterminate point from 12 µ s after the start of conversion N until BUSY rises, the internal logic shifts the results
of conversion N into the output register. If CS is low, R/ C high, and the external clock is high at this point, data is
lost. So, with CS low, either R/ C and/or DATACLK must be low during this period to avoid losing valid data.
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