Datasheet
www.ti.com
PARALLEL OUTPUT (After a Conversion)
R/C
BUSY
MODE
Parallel
Data Bus
BYTE
t
1
t
3
t
4
t
1
t
3
t
6
t
7
t
5
t
6
t
8
t
12
t
11
t
10
t
12
t
2
t
9
t
12
t
12
t
12
t
9
t
12
Previous
High Byte Valid
Hi-Z
Previous High
Byte Valid
Previous Low
Byte Valid
Not Valid
High Byte
Valid
Low Byte
Valid
Hi-Z
High Byte
Valid
Acquire Convert Acquire Convert
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
9
t
21
t
9
Hi-Z State High Byte Hi-Z State Low Byte Hi-Z State
t
4
t
3
t
1
R/C
BUSY
CS
Data Bus
BYTE
ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
Upon initial power up, the parallel output contains indeterminate data.
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N is available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
data. Refer to Table 5 and Figure 33 and Figure 34 for timing specifications.
Figure 33. Conversion Timing With Parallel Output ( CS and DATACLK Tied Low, EXT/INT Tied High)
Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs
14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS8506