Datasheet

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ADS8506
+5 V
+
+
Convert Pulse
40 ns Min
200 Ω
0.1 µF 10 µF
100 Ω
+
2.2 µF
66.5 kΩ
Serial Output
NC
(1)
BUSY
R/C
SDATA
± 10 V
+ 5 V
22 µF
+
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
DATACLK
STARTING A CONVERSION
ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
Figure 32. Basic ± 10-V Operation With Serial Output
The combination of CS (pin 23) and R/ C (pin 22) low for a minimum of 40 ns puts the sample-and-hold of the
ADS8506 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion N is
completed and the internal output register has been updated. All new convert commands during BUSY low are
ignored. CS and/or R/ C must go high before BUSY goes high, or a new conversion is initiated without sufficient
time to acquire a new signal.
The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 µ s between convert
commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS,
R/ C, and BUSY states, and Figure 33 , Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 , and Figure 39 for
timing diagrams.
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/ INT Tied High)
CS R/ C BUSY OPERATION
1 X X None. Data bus is in Hi-Z state.
↓ 0 1 Initiates conversion N. Data bus remains in Hi-Z state.
0 ↓ 1 Initiates conversion N. Databus enters Hi-Z state.
0 1 ↑ Conversion N completed. Valid data from conversion N on the databus.
↓ 1 1 Enables databus with valid data from conversion N.
↓ 1 0 Enables databus with valid data from conversion N – 1
(1)
. Conversion N in progress.
0 ↑ 0 Enables databus with valid data from conversion N – 1
(1)
. Conversion N in progress.
0 0 ↑ New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/ C
must be HIGH when BUSY goes HIGH.
X X 0 New convert commands ignored. Conversion N in progress.
(1) See Figure 33 and Figure 34 for constraints on data valid from conversion N – 1.
CS and R/ C are internally ORed and level triggered. It is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/ C initiates conversion N, be sure the less critical
input is low at least t
su2
≥ 10 ns prior to the initiating input. If EXT/ INT (pin 8) is low when initiating conversion N,
serial data from conversion N – 1 is output on SDATA (pin 19) following the start of conversion N. See Internal
Data Clock in the Reading Data section.
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