Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

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FEATURES APPLICATIONS

DESCRIPTION

Successive Approximation Register

Clock

Comparator

CDAC

Buffer

REF

CAP

40 kΩ

9.9 kΩ

Internal

+2.5 V Ref

6 kΩ

Parallel

and

Serial

Data

Out

Control

BUSYBUSY

DATACLK

TAG

20 kΩ

39.8 kΩ

EXT/IN

R/C

SB/BTC

BYTE

REFD

Parallel

Data

PWRD

SDATA

ADS8506

SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007

12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH

INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE

• Industrial Process Control

• 40-kHz Min Sampling Rate

• Test Equipment

• 4-V, 5-V, and ± 10-V Input Ranges

• Medical Equipment

• 73.9-dB SINAD with 10-kHz Input

• Data Acquisition Systems

• ± 0.45 LSB Max INL

• Digital Signal Processing

• ± 0.45 LSB Max DNL, 12-Bit No Missing Codes

• Instrumentation

• ± 5-mV BPZ, ± 0.5 PPM/ ° C BPZ Drift

• SPI Compatible Serial Output With

Daisy-Chain (TAG), SPI Master/Slave Feature

The ADS8506 is a complete low power, single 5-V

• Single 5-V Analog Supply

supply, 12-bit sampling analog-to-digital (A/D)

• Pin-Compatible With ADS7806 and 16-Bit

converter. It contains a complete 12-bit

ADS7807/8507

capacitor-based, successive approximation register

(SAR) A/D converter with sample and hold, clock,

• Uses Internal or External 2.5-V Reference

reference, and data interface. The converter can be

• Low Power Dissipation

configured for a variety of input ranges including ± 10

– 24 mW Typ, 30 mW Max at 40 KSPS

V, 4 V, and 5 V. For most input ranges, the input

voltage can swing to 25 V or – 25 V without damage

• 50- µ W Max Power Down Mode

to the converter.

• 28-Pin SO Package

A SPI compatible serial interface allows data to be

• Full Parallel Interface

synchronized to an internal or external clock. A full

• 2's Comp or BTC Output Code

parallel interface with BYTE select is also provided to

allow the maximum system design flexibility. The

ADS8506 is specified at 40 kHz sampling rate over

the industrial -40 ° C to 85 ° C temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 QSPI, SPI are trademarks of Motorola.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
ADS8506 SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE FEATURES APPLICATIONS • • • • • • • • • • • • • 1 2 • • • • • • • • 40-kHz Min Sampling Rate 4-V, 5-V, and ±10-V Input Ranges 73.9-dB SINAD with 10-kHz Input ±0.45 LSB Max INL ±0.45 LSB Max DNL, 12-Bit No Missing Codes ±5-mV BPZ, ±0.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM INL (LSB) NO MISSING CODE FULLSCALE ERROR (%) SPECIFICATION TEMPERATURE RANGE PACKAGE LEAD PACKAGE DESIGNATOR ADS8506IB ±0.45 12 ±0.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER DNL TEST CONDITIONS Differential linearity error No missing codes ADS8506IB ADS8506I MIN TYP MAX MIN TYP MAX -0.45 ±0.15 0.45 -0.9 ±0.15 0.9 12 Transition noise (2) 12 0.1 Gain Error -0.25 Full scale error drift -0.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER ADS8506IB TEST CONDITIONS MIN TYP ADS8506I MAX MIN TYP MAX UNIT Data format - Parallel 12-bits in 2-bytes Data coding - Serial binary 2s complement or straight binary VOL Low-level output voltage ISINK = 1.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Terminal Functions TERMINAL NO. NAME DIGITAL I/O DESCRIPTION 1 R1IN Analog Input. 2 AGND1 Analog sense ground. Used internally as ground reference point. Minimal current flow 3 R2IN Analog Input. 4 CAP Reference buffer output. 2.2-µF Tantalum capacitor to ground. 5 REF Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Table 1. Input Range Connections (see Figure 42 and Figure 43) ANALOG INPUT RANGE CONNECT R1IN VIA 200 Ω TO CONNECT R2IN VIA 100 Ω TO IMPEDANCE ±10 V VIN CAP 45.7 kΩ 0 V to 5 V AGND VIN 20.0 kΩ 0 V to 4 V VIN VIN 21.4 kΩ TYPICAL CHARACTERISTICS POWER SUPPLY CURRENT vs FREE-AIR TEMPERATURE INTERNAL REFERENCE vs FREE-AIR TEMPERATURE 4.5 4 2.510 2.505 2.500 2.495 2.490 2.485 5 4.5 4 3.5 10 2.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) UNIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE UNIPOLAR FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 3 1 0 -1 Unipolar Range, 4 V Input Range Unipolar Full-Scale Error - %FSR Unipolar Full-Scale Error - %FSR 0.1 0 -0.1 Unipolar Range, 5 V Input Range -0.1 -0.2 -0.3 -0.4 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC -0.
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ADS8506 www.ti.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) CONVERSION TIME vs FREE-AIR TEMPERATURE tCONVERT - Conversion Time - ms 13.6 13.5 13.4 13.3 13.2 13.1 13 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 Figure 25. INL 0.3 0.2 INL - LSBs 0.1 0 -0.1 -0.2 -0.3 0 512 1024 1536 2048 2560 3072 3584 4095 2560 3072 3584 4095 Code Figure 26. DNL 0.3 0.2 DNL - LSBs 0.1 0 -0.1 -0.2 -0.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) FFT 0 -10 8192 Point FFT, fi = 10 kHz, 0 dB Amplitude - dB -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 f - Frequency - kHz 15 20 15 20 Figure 28. FFT 0 -10 -20 8192 Point FFT, fi = 20 kHz, 0 dB Amplitude - dB -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 f - Frequency - kHz Figure 29.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight most significant bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the four least significant bits (LSBs) will be valid when BUSY rises. Data will be output in binary 2's complement (BTC) format. BUSY going HIGH can be used to latch the data.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Serial Output 200 Ω ± 10 V 66.5 kΩ +5V 100 Ω 2.2 µF 22 µF + + 1 28 2 27 3 26 4 25 5 24 6 23 7 22 ADS8506 + 0.1 µF + +5 V 10 µF BUSY Convert Pulse R/C 8 21 NC(1) 9 20 NC(1) 10 19 SDATA DATACLK NC(1) 11 18 NC(1) 12 17 NC(1) NC(1) 13 16 NC(1) 14 15 NC(1) 40 ns Min Figure 32.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This has no effect when using the internal data clock in the serial output mode. The parallel output and the serial output (only when using an external data clock), however, is affected whenever R/C goes high and the external clock is active. Refer to the Reading Data section.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Upon initial power up, the parallel output contains indeterminate data. PARALLEL OUTPUT (After a Conversion) After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid data from conversion N is available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the data. Refer to Table 5 and Figure 33 and Figure 34 for timing specifications.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 PARALLEL OUTPUT (During a Conversion) After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs after the start of conversion N. Do not attempt to read data beyond 12 µs after the start of conversion N until BUSY (pin 24) goes high; this may result in reading invalid data. Refer to Table 5 and Figure 33 and Figure 34 for timing constraints. Table 5.
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ADS8506 SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 www.ti.com EXTERNAL DATA CLOCK (After a Conversion) After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS low and R/C high, valid data from conversion N is output on SDATA (pin 19) synchronized to the external data clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the external data clock.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Table 6. Serial Timing Requirements, TA = –40°C to 85°C PARAMETER tw1 Pulse duration, convert td1 Delay time, BUSY from R/C low tw2 Pulse duration, BUSY low td2 Delay time, BUSY, after end of conversion td3 Delay time, aperture tconv Conversion time tacq Acquisition time tconv + tacq MIN TYP MAX 0.04 12 µs 12 20 ns 13.5 15 µs 5 ns 5 ns 13.5 10 UNIT 15 µs µs 11.
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ADS8506 www.ti.
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ADS8506 www.ti.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling period must be sufficiently long to allow all data words to be read before starting a new conversion.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 +15V 2.2 mF 22 pF ADS8506 200 W 100 nF GND R1IN 2 kW Pin 7 2 kW Vin Pin 2 22 pF Pin3 AGND1 Pin 1 100 W − OPA 627 or OPA 132 + R2IN Pin 6 33.2 kW GND R3IN Pin4 CAP 2.2 mF GND REF 2.2 mF GND 100 nF DGND 2.2 mF GND AGND2 −15 V GND Figure 41.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Software Calibration To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet specifications for offset and gain, the resistors shown in Figure 43 are necessary. See the No Calibration section for more details on the external resistors. Refer to Table 8 for the range of offset and gain errors with and without the external resistors. ±10 V VIN 0 V to 5 V 200 Ω 1 2 66.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 (a) Bipolar (b) Unipolar Digital Output Digital Output + Full-Scale + Full-Scale Analog Input − Full-Scale Analog Input − Full-Scale Typical Transfer Functions With External Resistors. Typical Transfer Functions Without External Resistors. Figure 44. Typical Transfer Functions With and Without External Resistors To further analyze the effects of removing any combination of the external resistors, consider Figure 45.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 REFERENCE The ADS8506 can operate with its internal 2.5-V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5% for low grade, ±0.25% for high grade).
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 7000 Power−Up Time − ms 6000 5000 4000 3000 2000 1000 0 0.1 1 10 CAP − Pin Value − mF 100 Figure 47. Power-Down to Power-Up Time vs Capacitor Value on CAP The output of the buffer is capable of driving up to 1 mA of current to a DC load. Using an external buffer allows the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP.
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ADS8506 SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 www.ti.com from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 APPLICATION INFORMATION AVERAGING The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√Hz where n is the number of averages. For example, averaging four conversion results reduces the TN by to 0.4 LSBs. Averaging should only be used for input signals with frequencies near DC.
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ADS8506 www.ti.com SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 Revision History Changes from Revision A (OCTOBER 2007) to Revision B ........................................................................................... Page • • • • • • • • • • • • • • • • • • 28 Changed minimum INL for ADS8506I from ±0.45 to ±0.9 LSB in ordering information table ............................................... 2 Changed INL min value for ADS8506I from -0.45 to -0.9 LSB in the electrical characteristics .....
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8506IBDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 ADS8506IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8506IBDWR SOIC DW 28 1000 367.0 367.0 55.0 ADS8506IDWR SOIC DW 28 1000 367.0 367.0 55.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.