Datasheet
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ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
DEVICE INFORMATION (continued)
Terminal Functions
TERMINAL
DIGITAL
DESCRIPTION
I/O
NAME DB/DW NO.
AGND1 2 Analog ground. Used internally as ground reference point.
AGND2 5 Analog ground.
BUSY 26 O At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
BYTE 23 I Selects 8 most significant bits (low) or 8 least significant bits (high).
CAP 4 Reference buffer capacitor. 2.2- µ F Tantalum capacitor to ground.
CS 25 I Internally ORed with R/ C. If R/ C is low, a falling edge on CS initiates a new conversion.
DGND 14 Digital ground.
D15 (MSB) 6 O Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS is
high, or when R/ C is low.
D14 7 O Data bit 14. Hi-Z state when CS is high, or when R/ C is low.
D13 8 O Data bit 13. Hi-Z state when CS is high, or when R/ C is low.
D12 9 O Data bit 12. Hi-Z state when CS is high, or when R/ C is low.
D11 10 O Data bit 11. Hi-Z state when CS is high, or when R/ C is low.
D10 11 O Data bit 10. Hi-Z state when CS is high, or when R/ C is low.
D9 12 O Data bit 9. Hi-Z state when CS is high, or when R/ C is low.
D8 13 O Data bit 8. Hi-Z state when CS is high, or when R/ C is low.
D7 15 O Data bit 7. Hi-Z state when CS is high, or when R/ C is low.
D6 16 O Data bit 6. Hi-Z state when CS is high, or when R/ C is low.
D5 17 O Data bit 5. Hi-Z state when CS is high, or when R/ C is low.
D4 18 O Data bit 4. Hi-Z state when CS is high, or when R/ C is low.
D3 19 O Data bit 3. Hi-Z state when CS is high, or when R/ C is low.
D2 20 O Data bit 2. Hi-Z state when CS is high, or when R/ C is low.
D1 21 O Data bit 1. Hi-Z state when CS is high, or when R/ C is low.
D0 (LSB) 22 O Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,
or when R/ C is low.
R/ C 24 I With CS low and BUSY high, a falling edge on R/ C initiates a new conversion. With CS
low, a rising edge on R/ C enables the parallel output.
REF 3 Reference input/output. 2.2- µ F Tantalum capacitor to ground.
V
ANA
27 Analog supply input. Nominally +5 V. Decouple to ground with 0.1- µ F ceramic and
10- µ F tantalum capacitors.
V
DIG
28 Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ V
ANA
.
V
IN
1 Analog input. See Figure 28 .
5
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