Datasheet

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3.1 Digital Control via J5, U4 and U6
3.2 Additional Digital Control and Monitoring
Digital Interface
J5 provides the parallel data bus control signals used on the various interface boards mentioned at the
beginning of this document. Two single "OR" gates (U4 and U6 - SN74AHC1G32) are provided to allow
several methods of accessing the converted analog signal.
U4 in conjunction with three pin jumper W5 (shunt pins 1-2) allows the user to write a conversion
command to the R/C pin of the data converter. When a valid chip select signal is applied to the ADC's CS
pin, the host processors write strobe ( WR/(R/W)) can be used to initiate a conversion cycle. This function
can be bypassed by placing a shunt jumper on J5 pins 3-4. For stand alone operation, the CS pin can be
held low by removing the shunt at W8 and applying the R/C strobe to J5, pin 17. The shunt on W5 needs
to be moved to cover pins 2-3 in this case. The signal on J5 pin 17 connects to one of the timer outputs of
the host DSP when this EVM is used with the 5-6K Interface Board. DSK users could set a periodic
function in the DSP to initiate the conversion cycle if desired.
U6 in conjunction with U3 (an SN74ALVCH16245) provides a means to isolate the ADC from the external
data bus. When a valid chip select is applied to the ADC, the host processors read strobe ( RD) enables
the outputs of the data buffer. This function can be bypassed by placing a shunt jumper on J5 pins 5-6.
Table 2. Pinnout of the Digital Control Connector, J5
Pin Signal / Function
1 DC_CSx - EVM Address Decoder Enable. Can be tied low by placing a shunt on J5 pins 1-2.
3 /WR(R/W) - Host processor active low write strobe
5 /RD - Host processor active low read strobe
7 EVM_A0 - used in conjunction with EVM_A1 and EVM_A2 to determine the ADC address on the data bus.
9 EVM_A1 - used in conjunction with EVM_A0 and EVM_A2 to determine the ADC address on the data bus.
11 EVM_A2 - used in conjunction with EVM_A0 and EVM_A1 to determine the ADC address on the data bus.
13 EVM_A3 - connects to the G1 enable of the address decoder U5. This pin must be high for address decoding
operations.
15 EVM_A4 - can be used to control BYTE mode data access
17 TOUT - When W5 is shunted pins 2-3, the signal applied to this pin can be used to initiate a conversion if the
ADC has been properly chip selected.
19 /INTB - the buffered BUSY signal output of the ADC. Can provide the host processor with an interrupt source.
2-20 (even) Digital Ground
Jumper W2 is provided along with a 10 k Ω resistor (R5) allowing the data converter installed at position
U1 to operate in BYTE mode. BYTE access requires two read accesses to the ADC in order to get the full
16-bit data output, once with BYTE high and again with BYTE low. When BYTE is low (default, W2
installed) the data is presented with the LS Byte on pins 22-15 and the MS Byte on pins 13-6. When
BYTE is high, the LS Byte and MS Byte swap. An eight bit processor can be configured to take LS or MS
data first using either side of the chip, simplifying board layout.
The digital control lines and parallel data bus can be monitored directly from J5 and J4. Each of these
connectors provides a complementary digital ground pin and can easily accomodata logic analysers or
oscilloscopes. Test points 1 through 4 provide access to analog and digital ground as well as the applied
power supply voltages. Test point 5 can be used to monitor the reference voltage.
ADS78/8505EVM User's GuideSLAU145 – December 2004 3