Datasheet

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2 Analog Interface
2.1 Optional Amplifier Input
3 Digital Interface
Analog Interface
For maximum flexibility, the ADS78/8505EVM is designed for easy interfacing to multiple analog sources.
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient ten-pin dual
row header/socket combination at J1. This header/socket provides access to the analog input pins of the
ADC. Please consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating
connector options. Table 1 shows the pin out of the analog input connector, J1.
Table 1. Pinout of the Analog Input Connector, J1
Pin Number Signal Description
J1.2 thru Analog To accommodate EVM Stacking using the SN74AHC138 address decoder, J1 feeds jumper W1. Up to
J1.16 (even) Input four converters can used at the same time.
J1.20 REF(+)J External reference source input, accessible through W4.
J1.15 REFOUT Optional connection via W4. Provides external AFE circuitry with REFOUT bias voltage.
J1.1- J1.19 AGND Analog ground connections. Note J1.15 is used for REFOUT connections to external AFE circuitry.
(odd)
The analog front-end (AFE) circuitry found on the EVM consists of a simple RC filter. When used in
combination with the 5-6K Interface Board, the circuits found on both DAP Signal Conditioning Boards
(see SLAU105 ) provide the level shifting and amplifier configurations to realize single ended or bi-polar
mode operation of the analog-to-digital converter installed on the EVM.
Jumper W6 provides access to an optional amplifier/buffer circuit on the front end of the data converter.
Component U8 can be installed at the user's option with any standard 8 pin SOIC single amplifier
component. The amplifier circuit is connected to the ± VA terminals for split supply operation. If single
supply amplifiers are used, the –VA (J3 pin 2) can be tied to analog ground (J3 pin 6). The footprint for
common 4mm trim pots (see component R7) is provided as an offset adjustment for precision amplifiers
such as the OPA228. When used in conjunction with the 5-6K Interface Board, please be aware that the
–VA supply is common to all power connectors (JP1 through JP6). Shorting the –VA supply to ground on
the ADS78/8505EVM is possible only if it is not used elsewhere on the interface board.
The active low CS pin is connected to W8. This pin can be controlled through the SN74AHC138 address
decoder at U5. For standalone operation, a 10K resistor to ground on the CS pin is provided. Completely
removing the shunt at W8 ensures this pin is held low.
The converted data output from the ADC is applied to U3, an SN74ALVCH16245. This 16-bit wide buffer
can be configured for 3.3 or 5.0V systems by providing the device with the appropriate IO voltage via W3
(see EVM silkscreen and schematic for details). The SN74ALVCH16245 features 5V tolerant inputs,
making it an ideal level shifting buffer for 3V processors. The entire 16 bit data output is presented to J4
pins 1-31 (odd). J4 is a header/socket combination which acts as a pass through connector for easy data
monitoring and/or board stacking when multiple devices share the data bus.
The BUSY signal is fed through a single gate buffer, an SN74AHC1G125, which is also supplied by the IO
voltage selected at W3. The BUSY signal can be used as an interrupt source to the host processor,
indicating the converted data is ready to be accessed through the parallel data buffer. The remaining
digital control lines are discussed in the following section.
ADS78/8505EVM User's Guide2 SLAU145 – December 2004