Datasheet

www.ti.com
t
h1
t
d5
t
h1
BYTE
BUS 18/16
RD = 0
DB[17:12]
D[17:12] D[9:4]
Previous LSB
DB[11:10]
D[11:10]
DB[9:0]
D[9:0]
D[3:2]
Next D[17:12]
D[1:0]
Next D[11:10]
Next D[9:0]
t
su5
t
su5
t
su5
t
su5
t
w1
t
w2
t
pd1
t
pd2
t
w4
t
(CONV)
t
w3
t
(CONV)
t
(ACQ)
CONVST
BUSY
CS = 0
SAMPLING
†
(When CS = 0)
CONVERT
†
t
pd3
t
pd3
t
(HOLD)
t
(HOLD)
†
Signal internal to device
t
su(ABORT)
t
su(ABORT)
ADS8484
SLAS511 – NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 34. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS8484