Datasheet

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Digital Interface
Read ( RD), conversion start ( CONVST) and reset ( RESET) signals to the converter can be assigned to
two different addresses in memory via jumper settings. This allows for the stacking of up to two
ADS8402EVM, ADS8406EVM, and/or ADS8412EVMs into processor memory. See Table 4 for jumper
settings. Note that the evaluation module does not allow the chip select ( CS) line of the converter to be
assigned to different memory locations. It is therefore suggested that the CS line be grounded or wired to
an appropriate signal of the processor.
Table 4. Jumper Settings for Decoder Outputs
Reference Description Jumper Settings
Designator
1-2 2-3
Set A[2..0]= 0x1 to generate RD pulse Installed
(1)
W2
Set A[2..0]=0x2 to generate RD pulse Installed
Set A[2..0]=0x3 to generate convst pulse Installed
(1)
W5
Set A[2..0]=0x4 to generate convst pulse Installed
Set A[2..0]=0x5 to generate RESET pulse Installed
(1)
W4
Set A[2..0]=0x6 to generate RESET pulse Installed
The data bus is available at connector P3; see Table 5 for pinout information.
(1) Factory Installed
Table 5. Data Bus Connector P3
(1)
Connector.Pin Signal Description
P3.1 D0 Buffered Data Bit 0 (LSB)
P3.3 D1 Buffered Data Bit 1
P3.5 D2 Buffered Data Bit 2
P3.7 D3 Buffered Data Bit 3
P3.9 D4 Buffered Data Bit 4
P3.11 D5 Buffered Data Bit 5
P3.13 D6 Buffered Data Bit 6
P3.15 D7 Buffered Data Bit 7
P3.17 D8 Buffered Data Bit 8
P3.19 D9 Buffered Data Bit 9
P3.21 D10 Buffered Data Bit 10
P3.23 D11 Buffered Data Bit 11
P3.25 D12 Buffered Data Bit 12
P3.27 D13 Buffered Data Bit 13
P3.29 D14 Buffered Data Bit 14
P3.31 D15 Buffered Data Bit 15
This evaluation module provides direct access to all the analog-to-digital converter control signals via
connector J3; see Table 6 .
(1) All even-numbered pins of P3 are tied to DGND.
SLAU126A – December 2003 – Revised September 2004 ADS8402/ADS8406/ADS8412 EVM User's Guide 5