Datasheet

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TIMING DIAGRAMS
t
w1
CONVST
t
pd1
t
pd2
t
w4
t
su1
BUSY
CS
CONVERT
†
t
CONV
SAMPLING
†
(When CS Toggle)
BYTE
t
w2
t
w3
t
ACQ
t
h1
t
d1
t
en
RD
t
dis
t
h2
t
su2
t
CONV
†
Signal internal to device
D [7:0]
Hi−Z Hi−Z
DB[15:8]
Hi−ZHi−Z
D [15:8]
D [7:0]
DB[7:0]
t
d6
t
su4
t
w7
t
d7
t
cycle
t
pd1
Data to
be read
†
Invalid
Previous Conversion Current Conversion
Invalid
t
h4
t
su5
(used in normal
conversion)
CONVST
(used in ABORT)
t
su(AB)
t
su(AB)
ADS8411
SLAS369B – APRIL 2002 – REVISED DECEMBER 2004
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
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