Datasheet

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TIMING CHARACTERISTICS
ADS8411
SLAS369B – APRIL 2002 – REVISED DECEMBER 2004
All specifications typical at –40 ° C to 85 ° C, +VA = +VBD = 5 V
(1) (2) (3)
PARAMETER MIN TYP MAX UNIT
t
CONV
Conversion time 340 400 ns
t
ACQ
Acquisition time 100 ns
t
pd1
CONVST low to BUSY high 30 ns
t
pd2
Propagation delay time, end of conversion to BUSY low 5 ns
t
w1
Pulse duration, CONVST low 20 ns
t
su1
Setup time, CS low to CONVST low 0 ns
t
w2
Pulse duration, CONVST high 20 ns
CONVST falling edge jitter 10 ps
t
w3
Pulse duration, BUSY signal low Min(t
ACQ
) ns
t
w4
Pulse duration, BUSY signal high 370 ns
Hold time, first data bus data transition ( RD low, or CS low for read
t
h1
40 ns
cycle, or BYTE input changes) after CONVST low
t
d1
Delay time, CS low to RD low (or BUSY low to RD low) 0 ns
t
su2
Setup time, RD high to CS high 0 ns
t
w5
Pulse duration, RD low 50 ns
t
en
Enable time, RD low (or CS low for read cycle) to data valid 20 ns
t
d2
Delay time, data hold from RD high 0 ns
t
d3
Delay time, BYTE rising edge or falling edge to data valid 2 20 ns
t
w6
Pulse duration, RD high 20 ns
t
w7
Pulse duration, CS high 20 ns
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
t
h2
50 ns
falling edge
t
su3
Setup time, BYTE transition to RD falling edge 0 ns
t
h3
Hold time, BYTE transition to RD falling edge 0 ns
t
dis
Disable time, RD high ( CS high for read cycle) to 3-stated data bus 20 ns
t
d5
Delay time, end of conversion to MSB data valid 10 ns
Byte transition setup time, from BYTE transition to next BYTE
t
su4
50 ns
transition
t
d6
Delay time, CS rising edge to BUSY falling edge 50 ns
t
d7
Delay time, BUSY falling edge to CS rising edge 50 ns
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
t
su(AB)
60 340 ns
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
t
su5
MAX(t
CONV
) + MAX(t
d5
) ns
current conversion
Hold time, data (MSB) from previous conversion hold valid from
t
h4
MIN(t
CONV
) ns
falling edge of CONVST
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagrams.
(3) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
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