Datasheet

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REFERENCE
ANALOG INPUT
DIGITAL INTERFACE
Timing And Control
ADS8411
SLAS369B – APRIL 2002 – REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The ADS8411 can operate with an external reference with a range from 3.9 V to 4.2 V. A 4.096-V internal
reference is included. When the internal reference is used, pin 2 (REFOUT) should be connected to pin 1
(REFIN) with 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and
48 (REFM) (see Figure 30). The internal reference of the converter is double buffered. If an external reference is
used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also
used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected
(floating) if an external reference is used.
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on
the internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input
to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to
V
ref
+ 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to V
ref
.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8411 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (100 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1
G Ω .
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different setting time. This may result in offset error,
gain error and linearity error which varies with temperature and input voltage.
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8411 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8411 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS
when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception ( CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
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