Datasheet

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†
Signal internal to device
CONVST
BUSY
CS = 0
CONVERT
†
SAMPLING
†
(When CS Toggle)
BYTE
RD = 0
t
w1
t
pd1
t
pd2
t
w4
t
w2
t
w3
t
CONV
t
ACQ
t
CONV
Invalid
DB[15:8]
DB[7:0]
MSB
LSB
t
d3
Previous
Previous
t
cycle
t
su(AB)
t
su(AB)
(used in normal
conversion)
CONVST
(used in ABORT)
t
su5
t
pd2
t
h1
t
h1
t
pd1
t
d3
t
d3
t
h4
LSB
Previous
t
d5
Invalid
MSB
MSB
MSB
MSB
Invalid
Invalid
LSB
t
h4
t
d5
t
su5
LSB
Valid
Hi−Z
t
en
t
dis
t
en
t
d3
t
dis
ValidValid
Hi−ZHi−Z
CS
RD
BYTE
DB[15:0]
t
su4
ADS8411
SLAS369B – APRIL 2002 – REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
Figure 5. Detailed Timing for Read Cycles
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