Datasheet

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†
Signal internal to device
t
CONV
CONVST
BUSY
CS = 0
CONVERT
†
SAMPLING
†
(When CS = 0)
BYTE
RD
t
w1
t
pd2
t
pd1
t
w4
t
w2
t
w3
t
CONV
t
(ACQ)
t
h1
t
h2
t
en
t
dis
D [7:0]
Hi−Z Hi−Z
DB[15:8]
Hi−ZHi−Z
D [15:8]
D [7:0]
DB[7:0]
t
su4
t
cycle
t
su(AB)
t
su(AB)
CONVST
(used in ABORT)
(used in normal
conversion)
t
pd1
Data to
be read
†
Invalid
Invalid
t
h4
t
su5
Previous Conversion Current Conversion
ADS8411
SLAS369B – APRIL 2002 – REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
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