Datasheet

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†
Signal internal to device
CONVST
BUSY
CS
CONVERT
†
SAMPLING
†
(When CS Toggle)
BYTE
RD = 0
t
w1
t
pd1
t
pd2
t
w4
t
w2
t
w3
t
su1
t
CONV
t
ACQ
t
CONV
t
h1
t
en
t
h2
t
dis
D [7:0]
Hi−Z
Hi−Z
DB[15:8]
Hi−Z
Hi−Z
D [15:8]
D [7:0]
DB[7:0]
t
d6
t
su4
t
w7
t
d7
D [15:8]
D [7:0]
t
dis
Hi−Z
Hi−Z
t
en
D [15:8]
D [7:0]
t
en
Previous
Previous
Repeated
Repeated
t
cycle
t
su(AB)
t
su(AB)
(used in normal
conversion)
CONVST
(used in ABORT)
Data to
be read
†
Invalid
Invalid
t
h4
t
su5
Previous Conversion Current Conversion
ADS8411
SLAS369B – APRIL 2002 – REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
10