Datasheet

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REFERENCE
ANALOG INPUT
_
+
THS4031
ADS8405
+IN
−IN
6800 pF
15 
0.1 F
1 F
0.1 F
1 F
15 V
−15 V
300 
300 
V
IN
G = +2
ADS8405
SLAS427 – DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The ADS8405 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal
reference is included. When an internal reference is used, pin 2 (REFOUT) should be connected to pin 1
(REFIN) with a 0.1-µF decoupling capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47
and 48 (REFM) (see Figure 32 ). The internal reference of the converter is double buffered. If an external
reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer
is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left
unconnected (floating) if an external reference is used.
When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to
reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to
V
ref
+ 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to V
ref
.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8405 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (150 ns) of the device. When the converter goes into hold mode, the input impedance is greater than 1 G Ω .
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different setting times. This may result in offset error,
gain error, and linearity error which varies with temperature and input voltage. A typical input circuit using TI's
THS4031 is shown in Figure 33 .
Figure 33. Using the THS4031 with the ADS8405
19