Datasheet

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PIN ASSIGNMENTS
ADS8382
26 27 28 25 22
23 24
CONVST
CS
FS
PD
BUSY
SDO
SCLK
AGND +VBD
BDGND
+VA
REFM
5
6
7
4
1
2
3
12
13
14
11
8
9
10
17
16
15
18
21
20
19
AGND
AGND
AGND
+VA
REFIN
REFOUT
NC
+IN
−IN
NC
+VA
AGND
AGND
AGND
+VA
+VA
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
TOP VIEW
TERMINAL FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
AGND 1, 2, 4, 5, – Analog ground pins. AGND must be shorted to analog ground plane below the device.
15, 18, 19
BDGND 21 – Digital ground for all digital inputs and outputs. BDGND must be shorted to the analog ground plane below
the device.
BUSY 22 O Status output. This pin is high when conversion is in progress.
CONVST 25 I Convert start. This signal is qualified with CS internally.
CS 26 I Chip select
FS 27 I Frame sync. This signal is qualified with CS internally.
+IN 11 I Noninverting analog input channel
–IN 12 I Inverting analog input channel
NC 10, 13 – No connection
PD 28 I Power down. Device resets and powers down when this signal is high.
REFIN 8 I Reference (positive) input. REFIN must be decoupled with REFM pin using 0.1- µ F bypass capacitor and
1- µ F storage capacitor.
REFM 7 I Reference ground. To be connected to analog ground plane.
REFOUT 9 O Internal reference output. Shorted to REFIN pin only when internal reference is used.
SCLK 24 I Serial clock. Data is shifted onto SDO with the rising edge of this clock. This signal is qualified with CS
internally.
SDO 23 O Serial data out. All bits except MSB are shifted out at the rising edge of SCLK.
+VA 3, 6, 14, – Analog power supplies
16, 17
+VBD 20 – Digital power supply for all digital inputs and outputs.
7