Datasheet

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TIMING CHARACTERISTICS
(1) (2) (3) (4)
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
ADS8382I/ADS8382IB
REF
PARAMETER UNIT
FIGURE
MIN TYP MAX
CONVERSION AND SAMPLING
t
d1
Delay time, conversion start command to conversion start (aperture delay) 10 ns 43,45
t
d2
Delay time, conversion end to BUSY fall 5 ns 43,44,45
t
d4
Delay time, conversion start command to BUSY rise 20 ns 43
t
d3
Delay time, CONVST rise to sample start 5 ns 45
t
d5
Delay time, CS fall to sample start 10 ns 45
t
d6
Delay time, conversion abort command to BUSY fall 10 ns 46
DATA READ OPERATION
t
d12
Delay time, CS fall to MSB valid 3 15 ns 47
t
d15
Delay time, FS rise to MSB valid 6 18 ns 48,49
t
d7
Delay time, BUSY fall to MSB valid (if FS is high when BUSY falls) 18 ns 49
t
d13
Delay time, SCLK rise to bit valid 2 10 ns 47,48,49
t
d14
Delay time, CS rise to SDO 3-state 6 ns 47
MISCELLANEOUS
t
d10
Delay time, PD rise to SDO 3-state 55 ns 55,56
Nap mode 300 ns 57
Delay time, total Full power down (external reference used with or without t
d11
+ 2x
56
t
d18
device resume 1-µF||0.1-µF capacitor on REFOUT) conversions
time
Full power down (internal reference used with or without
25
(4)
ms 55
1-µF||0.1-µF capacitor on REFOUT)
t
d11
Delay time, untrimmed circuit full power-down resume time 1 ms 55,56
Delay time, device Nap 200 ns 57
t
d16
power-down time
Full power down (internal/external reference used) 10 µs 55,56
Delay time, trimmed internal reference settling (either by turning on supply or
t
d17
4 ms 55
resuming from full power-down mode), with 1-µF||0.1-µF capacitor on REFOUT
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
(3) All digital output signals loaded with 10-pF capacitors.
(4) Including t
d11
, two conversions (time to cycle CONVST twice), and t
d17
.
6