Datasheet

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TIMING REQUIREMENTS
(1) (2) (3) (4) (5) (6)
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
ADS8382I/ADS8382IB
REF
PARAMETER UNIT
FIGURE
MIN TYP MAX
Conversion time 43,44,
t
conv
1000 1160 ns
45,46
t
acq1
Acquisition time in normal mode 0.5 1000 µs 43,44,46
t
acq2
Acquisition time in nap mode (t
acq2
= t
acq1
+ t
d18
) 0.8 1000 µs 45
CONVERSION AND SAMPLING
Quite sampling time (last toggle of interface signals to convert start 42,43,44,
t
quiet1
command)
(6)
30 ns 45,47,48,
49
Quite sampling time (convert start command to first toggle of interface 42,43,44,
t
quiet2
signals)
(6)
10 ns 45,47,48,
49
Quite conversion time (last toggle of interface signals to fall of BUSY)
(6)
42,43,44,
t
quiet3
600 ns
45,47,49
t
su1
Setup time, CONVST before BUSY fall 15 ns 43
t
su2
Setup time, CS before BUSY fall (only for conversion/sampling control) 20 ns 42,43
t
su4
Setup time, CONVST before CS rise (so CONVST can be recognized) 5 ns 43,44,46
t
h1
Hold time, CS after BUSY fall (only for conversion/sampling control) 0 ns 43
t
h3
Hold time, CONVST after CS rise 7 ns 45
t
h4
Hold time, CONVST after CS fall (to ensure width of CONVST_QUAL)
(4)
20 ns 44
t
w1
CONVST pulse duration 20 ns 45
t
w2
CS pulse duration 10 ns 43,44
Pulse duration, time between conversion start command and conversion
t
w5
1000 ns 46
abort command to successfully abort the ongoing conversion
DATA READ OPERATION
t
cyc
SCLK period 25 ns 47,48,49
SCLK duty cycle 40% 60%
t
su5
Setup time, CS fall before first SCLK fall 10 ns 47
t
su6
Setup time, CS fall before FS rise 7 ns 48,49
t
su7
Setup time, FS fall before first SCLK fall 7 ns 48,49
t
h5
Hold time, CS fall after SCLK fall 3 ns 47
t
h6
Hold time, FS fall after SCLK fall 7 ns 48,49
t
su2
Setup time, CS fall before BUSY fall (only for read control) 20 ns 42,47
t
su3
Setup time, FS fall before BUSY fall (only for read control) 20 ns 42,49
t
h2
Hold time, CS fall after BUSY fall (only for read control) 15 ns 42,47
t
h8
Hold time, FS fall after BUSY fall (only for read control) 15 ns 42,49
t
w2
CS pulse duration 10 ns 47
t
w3
FS pulse duration 10 ns 48,49
MISCELLANEOUS
t
w4
PD pulse duration for reset and power down 60 ns 55,56
All unspecified pulse durations 10 ns
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
(3) All digital output signals loaded with 10-pF capacitors.
(4) CONVST_QUAL is CONVST latched by a low value on CS (see Figure 41 ).
(5) Reference figure indicated is only a representative of where the timing is applicable and is not exhaustive.
(6) Quiet time zones are for meeting performance and not functionality.
5