Datasheet

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SPECIFICATIONS
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, f
SAMPLE
= 600 kHz,
unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down,
Table 2 .)
ADS8382IB ADS8382I
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
ANALOG INPUT
Full-scale
+IN – (–IN) –V
ref
V
ref
–V
ref
V
ref
V
input voltage
(1)
+IN –0.2 V
ref
+ 0.2 -0.2 V
ref
+ 0.2
Absolute input voltage V
–IN –0.2 V
ref
+ 0.2 -0.2 V
ref
+ 0.2
Input common mode
(V
ref
/2) –0.2 (V
ref
/2) +0.2 (V
ref
/2) –0.2 (V
ref
/2) +0.2 V
range
Sampling capacitance
(measured between +IN
40 40 pF
to AGND and -IN to
AGND)
Input leakage current 1 1 nA
SYSTEM PERFORMANCE
Resolution 18 18 Bits
No missing codes 18 17 Bits
Quiet zones observed –3 ±1.25 3 –5 5
LSB
INL Integral linearity
(2) (3) (4)
(18 bit)
Quiet zones not observed ±2
Quiet zones observed –1 ±0.6 1.5 –2 2.5
LSB
DNL Differential linearity
(3)
(18 bit)
Quiet zones not observed ±1.25
E
O
Offset error
(3)
–0.75 ±0.25 0.75 –1.5 1.5 mV
E
G
Gain error
(3) (5)
–0.075 0.075 -0.1 0.1 %FS
At DC 80 80
Common-mode rejection
CMRR dB
[+IN + (–IN)]/2 = 50 mV
p-p
ratio
55 55
at 1 MHz + DC of V
ref
/2
Noise At 00000H output code 40 40 µ V RMS
DC Power supply rejec-
PSRR At 10000H output code 55 55 dB
tion ratio
SAMPLING DYNAMICS
Conversion time 1.16 1.16 µ s
Acquisition time 0.50 1000 0.50 1000 µ s
Throughput rate 600 600 kHz
Aperture delay 10 10 ns
Aperture jitter 12 12 ps RMS
Step response
(6)
400 400 ns
Overvoltage recovery 400 400 ns
DYNAMIC CHARACTERISTICS
VIN = 8 V
p-p
at 1 kHz -116 -116
Total harmonic
THD VIN = 8 V
p-p
at 10 kHz -115 -115 dB
distortion
(3) (7)
VIN = 8 V
p-p
at 100 kHz -96 -96
VIN = 8 V
p-p
at 1 kHz 96 96
SNR Signal-to-noise ratio
(3)
VIN = 8 V
p-p
at 10 kHz 95 95 dB
VIN = 8 V
p-p
at 100 kHz 94 94
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured using analog input circuit in Figure 54 and digital stimulus in Figure 58 and Figure 59 and reference voltage of 4.096 V.
(4) This is endpoint INL, not best fit.
(5) Measured using external reference source so does not include internal reference voltage error or drift.
(6) Defined as sampling time necessary to settle an initial error of 2Vref on the sampling capacitor to a final error of 1 LSB at 18-bit level.
Measured using the input circuit in Figure 54 .
(7) Calculated on the first nine harmonics of the input frequency.
3