Datasheet

www.ti.com
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
LAYOUT (continued)
As with the AGND connections, +VA should be connected to a +5-V power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. Power to the ADS8382
should be clean and well bypassed. A 0.1- µ F ceramic bypass capacitor should be placed as close to the device
as possible. See Table 3 for the placement of these capacitors. In addition, a 1- µ F capacitor is recommended. In
some situations, additional bypassing may be required, such as a 100- µ F electrolytic capacitor or even a Pi filter
made up of inductors and capacitors—all designed to essentially low-pass filter the +5-V supply, removing the
high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE
Pair of pins requiring a shortest (2,3); (5,6); (15,16); (17,18) (20,21)
path to decoupling capacitors
Pins requiring no decoupling 1, 4, 14, 19
When using the internal reference, ensure a shortest path from REFOUT (pin 9) to REFIN (pin 8) with the bypass
capacitor directly between pins 8 and 7.
26