Datasheet

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NAP MODE
Full I
CC
SDO
BUSY
LSB
SAMPLENAPCONVERTSAMPLE
LSB+1 MSB MSB−1
Hi−Z
t
CONV
t
d16
t
d18
I
CC
NAP
Full I
CC
PD = 0
CONVST
CS
CONVST_QUAL
DEVICE
STATE
REFIN
(or REFOUT)
I
CC
LAYOUT
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
Nap mode is automatically inserted at the end of a conversion if CONVST_QUAL is held low at EOC. The device
can be operated in nap mode at the end of every conversion for saving power at lower throughputs. Another way
to use this mode is to convert multiple times and then enter nap mode. The minimum sampling time after a nap
state is t
acq1
+ t
d18
= t
acq2
.
Figure 57. Device Nap Power Down/Resume
For optimum performance, care should be taken with the physical layout of the ADS8382 circuitry.
Since the ADS8382 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more the digital logic in the design and the
higher the switching speed, the greater the need for better layout and isolation of the critical analog signals from
these switching digital signals.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to the end of sampling and just prior to the latching of the
analog comparator. Such glitches might originate from switching power supplies, nearby digital logic, or high
power devices. Noise during the end of sampling and the latter half of the conversion must be kept to a minimum
(the former half of the conversion is not very sensitive since the device uses a proprietary error correction
algorithm to correct for the transient errors made here).
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing and
degree of the external event.
On average, the ADS8382 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external, it must be ensured that the reference source can drive the
bypass capacitor without oscillation. A 0.1- µ F bypass capacitor is recommended from pin 8 directly to pin 7
(REFM).
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
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