Datasheet

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ADS8382
+IN
−IN
THS4031
THS4031
20 
20 
1.5 nF
50 
50 
Input
Signal
(V+)
Input
Signal
(V−)
8 V
PP
, 2 V
Common
Mode
DIGITAL INTERFACE
TIMING AND CONTROL
READING DATA
POWER SAVING
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
THEORY OF OPERATION (continued)
Figure 54. Differential Input, Differential Output Configuration
Conversion and sampling are controlled by the CONVST and CS pins. See the timing diagrams for detailed
information on timing signals and their requirements. The ADS8382 uses an internally generated clock to control
the conversion rate and in turn the throughput of the converter. SCLK is used for reading converted data only. A
clean and low jitter conversion start command is important for the performance of the converter. There is a
minimal quiet zone requirement around the conversion start command as mentioned in the timing requirements
table.
The ADS8382 offers a high speed serial interface that is compatible with the SPI protocol. The device outputs
the data in 2's complement format. Refer to Table 1 for the ideal output codes.
Table 1. Input Voltages and Ideal Output Codes
DESCRIPTION ANALOG VALUE +IN – (–IN) DIGITAL OUTPUT (HEXADECIMAL)
Full-scale range 2(+V
REF
)
Least significant bit (LSB) 2(+V
REF
)/2
18
Full scale V
REF
– 1 LSB 1FFFF
Mid scale 0 00000
Mid scale – 1 LSB 0 V – 1 LSB 3FFFF
–Full scale –V
REF
20000
To avoid performance degradation due to the toggling of device buffers, read operation must not be performed in
the specified quiet zones (t
quiet1
, t
quiet2
, and t
quiet3
). Internal to the device, the previously converted data is updated
with the new data near the fall of BUSY. Hence, the fall of CS and the fall of FS around the fall of BUSY is
constrained. This is specified by t
su2
, t
su3
, t
h2
, and t
h8
in the timing requirements table.
The converter provides two power saving modes, full power down and nap. Refer to Table 2 for information on
activation/deactivation and resumption time for both modes.
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