Datasheet

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ADS8382
AGND
+VA
_
+
53 
53 
40 pF 40 pF
+IN
−IN
AGND
ANALOG INPUT
ADS8382
+IN
−IN
THS4031
THS4031
20 
20 
1.5 nF
50 
600 
600 
2 V
Input
Signal
(0 to 4 V)
AGND
4 V
PP
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
THEORY OF OPERATION (continued)
Figure 52. Simplified Analog Input
When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the
internal capacitor array. Both the +IN and –IN inputs have a range of –0.2 V to (+V
REF
+ 0.2 V). The input span
(+IN – (–IN)) is limited from –V
REF
to V
REF
.
The input current on the analog inputs depends upon throughput and the frequency content of the analog input
signals. Essentially, the current into the ADS8382 charges the internal capacitor array during the sampling
(acquisition) time. After this capacitance has been fully charged, there is no further input current. The source of
the analog input voltage must be able to charge the device sampling capacitance (40 pF each from +IN/–IN to
AGND) to an 18-bit settling level within the sampling (acquisition) time of the device. When the converter goes
into hold mode, the input resistance is greater than 1 G Ω .
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN, –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are
matched. If this is not observed, the two inputs can have different settling times. This can result in offset error,
gain error, and linearity error which vary with temperature and input voltage.
A typical input circuit using TI's THS4031 is shown in Figure 53 . In the figure, input from a single-ended source is
converted into a differential signal for the ADS8382. In the case where the source is differential, the circuit in
Figure 54 may be used. Most of the specified performance figure were measured using the circuit in Figure 54 .
Figure 53. Single-Ended Input, Differential Output Configuration
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