ADS8381EVM User’s Guide September 2004 Data Acquistion SLAU133A
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of ±6 V and the output voltage range of 0 V and 5.5 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Related Documentation From Texas Instruments Preface Read This First About This Manual This users guide describes the characteristics, operation, and use of the ADS8381 18-bit, 580-kHz, parallel interface, analog-to-digital converter evaluation board. A complete circuit description, schematic diagram, and bill of materials are included.
Contents FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
Contents Contents 1 EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Signal Conditioning . . . . . . . .
Contents Figures 2−1 6−1 6−2 6−3 6−4 Input Buffer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Layer—Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Plane—Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Plane—Layer 3 . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 EVM Overview This chapter contains the features of the ADS8381EVM. Topic 1.1 Page Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features 1.1 Features - Full-featured evaluation board for the high-speed ADS8381 18-bit, single channel, parallel interface, SAR-type analog-to-digital converters.
Chapter 2 Analog Interface The ADS8381 analog-to-digital converter has both a positive and negative analog input pin. Ground for the negative input is provided on the EVM (via SJP3) close the device, or a user-furnished ground wire may be attached. The negative input pin has a range of –200 mV up to 200 mV, and is shorted on the EVM via SJP3. A signal for the positive input pin can be applied at connector P1, pin 2 (shown in Table 2−1 ), or applied to the center pin of SMA connector J2. Table 2−1.
Signal Conditioning 2.1 Signal Conditioning The factory recommends the analog input to any SAR-type converter be buffered and low-pass filtered. It is important to note that the input buffer circuit of the ADS8381EVM, shown in Figure 2−1, uses the THS4031 in an inverting gain-of-one configuration. The amplifier is not stable in a conventional gain-of-one configuration. The THS4031 was selected for its low noise, high slew rate, and fast settling time.
Reference 2.2 Reference The ADS8381EVM provides an onboard 4.096-V reference circuit. This reference voltage can be applied directly to the VREF pin of the converter; it does not need to be buffered. The EVM also has provision for a user-supplied external reference voltage. This voltage can be filtered, as needed, by routing the signal through amplifier U1. The EVM allows users to select from two reference sources.
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Chapter 3 Digital Interface The ADS8381EVM is designed for easy interfacing to multiple platforms. Samtec part numbers SSW−110−22−F−D−VS−K and TSM−110−01−T−DV−P provide a convenient dual-row-header/socket combination at P2 and P3. Consult Samtec at www.samtec.com or 1−800−SAMTEC−9 for a variety of mating connector options. Table 3−1. Pinout for Parallel Control Connector P2 Connector.Pin Signal P2.1 DC_CS Description Daughtercard Board Select pin P2.3 P2.5 P2.7 A0 Address line from processor P2.
Table 3−2. Jumper Settings Jumper Settings Reference Designator W1 W2 W3 † Description 1−2 2−3 Set A[2..0] = 0x1 to generate RD pulse Installed † Not installed Set A[2..0] = 0x2 to generate RD pulse Not installed Installed Set A[2..0] = 0x3 to generate CONVST pulse Installed † Not installed Set A[2..
Chapter 4 Power Supply Requirements The EVM accepts four power supplies. - A dual ±Vs DC supply for the dual supply op amps. Recommend a ±6-VDC supply. - A single +5.0-VDC supply for analog section of the board (A/D + Refer- ence). - A single +5.0-V or +3.3-VDC supply for digital section of the board (A/D + address decoder + buffers). There are two ways to provide these voltages. 1) Wire in the voltages at test points on the EVM. See Table 4−1. Table 4−1.
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Chapter 5 Using the EVM The ADS8381EVM serves three functions 1) As a reference design 2) As a prototype board and 3) As software test platform Topic Page 5.1 As a Reference Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 As a Prototype Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 As a Software Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
As a Reference Board 5.1 As a Reference Board As a reference design, the ADS8381EVM contains the essential circuitry to showcase the analog-to-digital converter. This essential circuitry includes the input amplifier, reference circuit, and buffers. The EVM analog input circuit is optimized for a 100-kHz sine wave; therefore, users may need to adjust the resistor and capacitor values of the A/D input RC circuit.
Chapter 6 ADS8381EVM BOM, Layout, and Schematic This chapter contains the ADS8381EVM bill of materials, the layouts, and the schematic. Topic Page 6.1 ADS8381EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 ADS8381EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3 ADS8381EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADS8381EVM Bill of Materials 6.1 ADS8381EVM Bill of Materials Table 6−1 contains a complete bill of materials for the ADS8381EVM. The schematic diagram also is provided for reference. Contact the Product Information Center or send an e−mail to dataconvapps@list.ti.com for questions regarding this EVM. Table 6−1.
ADS8381EVM Bill of Materials Reference Designator QTY Value Footprint Mfr Mfr’s Part Number Description C7, C9, C15, C22, C32, C34, C36 7 0.1 µF 805 Kemet or Alternate C0805C104J5RACTU Capacitor, 0.1 µF 50 V ceramic X7R 0805 C8, C16, C31, C37 4 1 µF 805 Panasonic − ECG or Alternate ECJ−GVB1C105K Capacitor, 1 µF 16 V ceramic X5R 0805 C2, C28 2 1 µF 1206 Kemet or Alternate C1206C105K3RACTU Capacitor, 1.0 µF 25 V ceramic X7R 1206 C33 1 0.
ADS8381EVM Bill of Materials Reference Designator QTY Value Footprint Mfr Mfr’s Part Number Description U9 1 SOIC−8 Footprint 8−SOP(D) Not installed Not installed Footprint for 8-pin SOIC reference operates from +5 V.
ADS8381EVM Layout 6.2 ADS8381EVM Layout Figure 6−1. Top Layer—Layer 1 Figure 6−2.
ADS8381EVM Layout Figure 6−3. Power Plane—Layer 3 Figure 6−4.
ADS8381EVM Schematic 6.3 ADS8381EVM Schematic The schematic follows this page.
1 2 3 4 5 6 Revision History REV ECN Number Approved D D J2 Analog-to-Digital Converter P1 EXT_REF DB[17...0] +IN BUSY 2 4 6 8 10 12 14 16 18 20 B_CS B_RD B_CONVST B_BYTE B_BUS18/16 1 3 5 7 9 11 13 15 17 19 DB[17..0] Analog Input Power & Digital Buffer C C +VA +VA TP18 2 4 6 8 10 -VA AGND -VA TP19 +5VD W4 TP16 +BVDD A0 A1 A2 INTc +3.3VD 1 3 5 7 9 B_DB[17...0] DC_CS +VA +5VA DGND -VA ADC_CS ADC_RD ADC_CONVST BYTE BUS18/16 B_BUSY TP15 J1 DB[17...
1 2 3 4 5 6 Revision History REV ECN Number Approved EXT_REF TP9 3 D D R15 +VCC 1 100 +5VCC C63 0.47uF +5VCC C16 1uF U3 1 C36 0.1uF GND 0.1uF 2 OUT SJP1 3 47uF 2 R14 6 1 OPA627 2 4 1 2 C C45 NI C18 3 NI 4 NC +VIN EN GND NC VREF NC IN GND OUT 100 R25 +VBD 2 NI SJP5 C8 1uF 7 C43 C21 0.1uF 0.01uF C48 C42 0.1uF C13 1 2 3 4 5 6 7 8 9 10 11 12 0.01uF 5 NI R21 0 +5VCC C47 2 0.
1 2 3 4 5 6 Revision History TP6 +5VA REV +5VCC L3 +5VA ECN Number Approved BLM21AJ601SN1L + C14 C9 10uF C12 10uF C11 C10 0.1uF 0.01uF 1000nF +VBD TP5 D +VBD U8 B_RD /OE VCC DIR D C59 0.1uF TP8 +BVDD A1 A2 A3 A4 A5 A6 A7 A8 +VBD L4 +BVDD RP4 BLM21AJ601SN1L + C24 C19 C22 10uF 10uF DB0 DB1 C23 C20 0.1uF 0.01uF 1000nF B1 B2 B3 B4 B5 B6 B7 B8 B_DB0 B_DB1 1K GND TP7 +VBD U7 B_RD TP3 +VA + C29 C28 10uF C6 1uF 10uF C4 C5 0.01uF 1000nF DB[17...
