Datasheet

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SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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6
TIMING CHARACTERISTICS
All specifications typical at −40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)
PARAMETER MIN TYP MAX UNIT
t
CONV
Conversion time 1.13 µs
t
ACQ
Acquisition time 0.2 µs
t
HOLD
Sampling capacitor hold time 25 ns
t
pd1
CONVST low to conversion started (BUSY high) 45 ns
t
pd2
Propagation delay time, End of conversion to BUSY low 20 ns
t
pd3
Propagation delay time, from start of conversion (internal state) to rising edge of BUSY 20 ns
t
w1
Pulse duration, CONVST low 40 400 ns
t
su1
Setup time, CS low to CONVST low 20 ns
t
w2
Pulse duration, CONVST high 20 ns
CONVST falling edge jitter 10 ps
t
w3
Pulse duration, BUSY signal low Min(t
ACQ
) µs
t
w4
Pulse duration, BUSY signal high 1.13 µs
t
h1
Hold time, First data bus data transition (CS low for read cycle, or RD or BYTE input
changes) after CONVST low
40 400 ns
t
d1
Delay time, CS low to RD low 0 ns
t
su2
Setup time, RD high to CS high 0 ns
t
w5
Pulse duration, RD low time 50 ns
t
en
Enable time, RD low (or CS low for read cycle) to data valid 20 ns
t
d2
Delay time, data hold from RD high 5 ns
t
d3
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 20 ns
t
w6
Pulse duration, RD high 20 ns
t
w7
Pulse duration, CS high time 20 ns
t
h2
Hold time, last CS rising edge or changes of RD or BYTE to CONVST falling edge 125 ns
t
pd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
Max(t
d5
) ns
t
su3
Setup time, BYTE transition to RD falling edge 10 ns
t
h3
Hold time, BYTE transition to RD falling edge 10 ns
t
dis
Disable time, RD High (CS high for read cycle) to 3-stated data bus 20 ns
t
d5
Delay time, BUSY low to MSB data valid 30 ns
t
su5
Setup time, BYTE transition to next BYTE transition 50 ns
t
su(AB)
Setup time, from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next
falling edge of CS (when CS is used to abort).
65 700 ns
t
f(CONVST)
Falling time, (CONVST falling edge) 10 30 ns
t
su6
Setup time, CS falling edge to CONVST falling edge when RD = 0 125 ns
(1)
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2 except for CONVST.
(2)
See timing diagrams.
(3)
All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.