Datasheet

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SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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Reading Data
The ADS8371 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when
CS
and RD are both low. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for
multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus.
Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION ANALOG VALUE
DIGITAL OUTPUT
Full scale range (+V
ref
)
DIGITAL OUTPUT
STRAIGHT BINARY
Least significant bit (LSB) (+V
ref
)/65536 BINARY CODE HEX CODE
+Full scale (+V
ref
) – 1 LSB 1111 1111 1111 1111 FFFF
Midscale (+V
ref
)/2 1000 0000 0000 0000 8000
Midscale – 1 LSB (+V
ref
)/2 – 1 LSB 0111 1111 1111 1111 7FFF
Zero 0 V 0000 0000 0000 0000 0000
The output data is a full 16-bit word (D15−D0) on DB15–DB0 pins (MSB−LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15−DB8. In this case
two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins
DB15−DB8, then bringing BYTE high. When BYTE is high, the low bits (D7−D0) appear on pins DB15−D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Table 2. Conversion Data Readout
BYTE
DATA READ OUT
BYTE
DB15−DB8 PINS DB7−DB0 PINS
High D7−D0 All one’s
Low D15−D8 D7−D0
RESET
The device can be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at
high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter.
D Issue a CONVST when CS is low and internal CONVERT state is high. The falling edge of CONVST starts a
reset.
D Issue a CS (select the device) while internal CONVERT state is high. The falling edge of CS causes a reset.
Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new
sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset.
INITIALIZATION
At first power on there are three read cycles required (RD must be toggled three times). If conversion cycle is
attempted before these initialization read cycles, the first three conversion cycles will not produce valid results. This
is used to load factory trimming data for a specific device to assure high accuracy of the converter. Because of this
requirement, the RD pin cannot be tied permanently to BDGND. System designers can still achieve the AUTO READ
function if the power-on requirement is satisfied.