Datasheet

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SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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26
Digital Inputs
The converter switches from sample to hold mode at the falling edge of the CONVST
input pin. A clean and low jitter
falling edge is important to the performance of the converter. A sharp falling transition on this pin can affect the voltage
that is acquired by the converter. A falling transition time in the range of 10 ns to 30 ns is required to achieve the rated
performance of the converter. A resistor of approximately 1000 Ω (10% tolerance) can be placed in series with the
CONVST input pin to satisfy this requirement.
The other digital inputs to the ADS8371 do not require any resistors in series with them. However, certain precautions
are necessary to ensure that transitions on these inputs do not affect converter performance. It is recommended that
all activity on the input pins happen during the first 400 ns of the conversion period. This allows the error correction
circuits inside the device to correct for any errors that these activities cause on the converter output. For example,
when the converter is operated with CS and RD tied to ground, the signal CONVST can be brought low to initiate
a conversion and brought high after a duration not exceeding 400 ns. Figure 41 shows the recommended timing for
the CONVST input with RD and CS tied low.
t
conv
CONVST
BUSY
CS = 0
RD = 0
400 ns
730 ns
(1)
125 ns
(1)
t
acq
(1)
Quiet Zone (No bus activity)
t
w1 < 400 ns
Figure 41. Timing for CONVST When CS = RD = BDGND