Datasheet

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SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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25
_
+
−IN
+IN
ADS8371
_
+
50 Ω
THS4031
15 Ω
200 pF
Unipolar Input
Figure 39. Unipolar Input to Converter
In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC
bias applied to its + input so as to keep the input to the ADS8371 within its rated operating voltage range. This
configuration is also recommended when the ADS8371 is used in signal processing applications where good SNR
and THD performance is required. The DC bias can be derived from the REF3020 or the REF3040 reference voltage
ICs. The input configuration shown below is capable of delivering better than 87-dB SNR and –90-db THD at an input
frequency of 100 kHz. In case bandpass filters are used to filter the input, care should be taken to ensure that the
signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal.
In such cases, the gain of the circuit shown in Figure 40 can be increased to keep the input to the ADS8371 large
to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031
in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output
of the REF3020 or REF3040 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of
the converter within its rated operating range.
_
+
−IN
+IN
ADS8371
_
+
360 Ω
THS4031
100 Ω
33 nF
Vdc
360 Ω
Vac
Figure 40. Bipolar Input to Converter
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their requirements.
The ADS8371 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 40 ns (after the 40 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The BUSY output is brought high
immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when
the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with
the falling edge of CS when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST
goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus
with the conversion.