Datasheet

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SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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PRINCIPLES OF OPERATION
The ADS8371 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 38 for
the application circuit for the ADS8371.
The conversion clock is generated internally. The conversion time of 1.13 µs is capable of sustaining a 750-kHz
throughput.
The analog input is provided to two input pins: +IN and −IN. When a conversion is initiated, the differential input on
these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected
from any internal function.
REFERENCE
The ADS8371 can operate with an external reference with a range from 2.5 V to 4.2 V. The reference voltage on the
input pin 1 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on
this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3040
can be used to drive this pin. A 0.1-uF decoupling capacitor is required between pin 1 and pin 48 of the converter.
This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize
the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network
can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-uF capacitor, which can also serve
as the decoupling capacitor, can be used to filter the reference voltage.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and −IN inputs is captured on the
internal capacitor array. The voltage on the −IN input is limited between –0.2 V and 0.2 V, allowing the input to reject
small signals which are common to both the +IN and −IN inputs. The +IN input has a range of –0.2 V to V
ref
+ 0.2 V.
The input span (+IN − (−IN)) is limited to 0 V to V
ref
.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8371 charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage
must be able to charge the input capacitance (45 pF) to an 16-bit settling level within the acquisition time (200 ns)
of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN
and −IN inputs and the span (+IN − (−IN)) should be within the limits specified. Outside of these ranges, the
converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters
should be used.
Care should be taken to ensure that the output impedance of the sources driving the +IN and −IN inputs are matched.
If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and
linearity error which changes with temperature and input voltage.
The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC
filter is recommended at the input pins to low-pass filter the noise from the source. A series resistor of 15 Ω and a
decoupling capacitor of 200 pF is recommended.
The input to the converter is a unipolar input voltage in the range 0 V to V
ref
. The THS4031 can be used in the source
follower configuration to drive the converter.