Datasheet


SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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13
t
d5
RD = 0
DB[15:8]
D[15:8]
DB[7:0]
D[7:0]
Next D[15:8]
Next D[7:0]
D[7:0]
t
su5
t
su5
Previous D[7:0]
†
Signal internal to device
t
w1
t
w2
t
pd1
t
pd2
t
w4
t
CONV
t
w3
t
CONV
t
(ACQ)
t
h1
t
h1
CONVST
BUSY
CS = 0
SAMPLING
†
(When CS = 0)
BYTE
CONVERT
†
t
dis
t
su5
t
su5
t
pd3
t
pd3
t
HOLD
t
HOLD
t
su(AB)
t
su(AB)
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
Valid
Hi−Z
t
en
t
dis
t
en
t
d3
t
dis
ValidValid
Hi−ZHi−Z
CS
RD
BYTE
DB[15:0]
t
su4
Figure 5. Detailed Timing for Read Cycles