Datasheet


SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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12
†
Signal internal to device
t
CONV
CONVST
BUSY
CS = 0
CONVERT
†
SAMPLING
†
(When CS = 0)
BYTE
RD
t
w1
t
pd2
t
pd1
t
w4
t
w2
t
w3
t
CONV
t
(ACQ)
t
h1
t
pd4
t
h2
t
en
t
dis
t
su5
t
HOLD
t
su(AB)
t
su(AB)
t
pd3
DB[15:8]
DB[7:0]
D[7:0]
D[15:8]
D[7:0]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
t
su5
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling