Datasheet


SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
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11
†
Signal internal to device
CONVST
BUSY
CS
CONVERT
†
SAMPLING
†
(When CS Toggle)
t
w1
t
pd1
t
pd2
t
w4
t
w2
t
w3
t
su6
t
CONV
t
ACQ
t
CONV
t
w7
t
pd3
t
HOLD
t
su(AB)
t
su(AB)
t
su6
t
pd4
RD = 0
t
en
t
dis
t
h2
t
su2
DB[15:8]
DB[7:0]
D[7:0]
D[15:8]
D[7:0]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
BYTE
t
h1
t
su5
t
su5
t
en
t
su5
t
en
t
su5
D [15:8]
Previous
D [7:0]
Previous
D [15:8]
t
dis
Hi−Z
Previous
D [7:0]
Hi−Z
Previous
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND