Datasheet


SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005
www.ti.com
10
TIMING DIAGRAMS
t
w1
CONVST
t
pd1
t
pd2
t
w4
t
su1
BUSY
CS
CONVERT
†
t
CONV
SAMPLING
†
(When CS Toggle)
BYTE
t
w2
t
w3
t
ACQ
t
h1
t
CONV
t
su5
t
w7
t
pd3
t
HOLD
t
su(AB)
t
su(AB)
t
pd4
t
en
RD
t
d1
t
dis
t
h2
t
su2
DB[15:8]
DB[7:0]
D[7:0]
D[15:8] D[7:0]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
t
su5
t
su5
t
su5
†
Signal internal to device
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling