SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 FEATURES D 750-KSPS Sample Rate D High Linearity: D D D D D D D D D D APPLICATIONS − +0.9 LSB INL Typ, +1.5 LSB Max − −0.4/+0.6 LSB DNL Typ, +1 LSB Max Onboard Reference Buffer and Conversion Clock 0 V to 4.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ADS8371I ADS8371IB MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±2.5 −1/1.5 ±1.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPECIFICATIONS TA = −40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 750 kHz (unless otherwise noted) ADS8371IB ADS8371I TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT Analog Input Full-scale input voltage (see Note 1) Absolute input voltage +IN − −IN 0 +IN −0.2 Vref Vref + 0.2 −IN −0.2 0.2 Input capacitance Input leakage current 0 −0.2 Vref Vref + 0.2 −0.2 0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPECIFICATIONS (CONTINUED) TA = −40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 750 kHz (unless otherwise noted) ADS8371IB ADS8371I TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP UNIT MAX UNIT Dynamic Characteristics Total harmonic distortion (THD) (see Note 1) Signal to noise ratio (SNR) (see Note 1) 1 kHz −106 −100 10 kHz −99 −96 50 kHz −92 −90 100 kHz −90 −88 1 kHz 87.7 87 10 kHz 87.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPECIFICATIONS (CONTINUED) TA = −40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 750 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Input/Output Logic family Logic level CMOS VIH VIL IIH = 5 µA IIL = 5 µA VOH VOL IOH = 2 TTL loads IOL = 2 TTL loads +VBD−1 +VBD + 0.3 0.8 −0.3 V +VBD − 0.6 0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TIMING CHARACTERISTICS All specifications typical at −40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3) PARAMETER MIN TYP MAX UNIT 1.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TIMING CHARACTERISTICS All specifications typical at −40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3) PARAMETER MIN TYP MAX UNIT 1.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 PIN ASSIGNMENTS BUSY NC NC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND PFB PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 3 4 5 6 7 8 13 9 10 11 12 REFIN NC NC +VA AGND +IN −IN AGND +VA +VA 1 2 NC − No connection.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TERMINAL FUNCTIONS NAME AGND BDGND NO. I/O 5, 8, 11, 12, 14, 15, 44, 45 − Analog ground DESCRIPTION 25, 38 − Digital ground for buffer supply BUSY 36 O Status output. High when a conversion is in progress. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 CS tpd3 CONVERT† tHOLD tCONV tCONV SAMPLING† (When CS Toggle) tACQ BYTE tsu(AB) tsu(AB) tsu5 th1 tsu5 tsu5 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[15:8] Hi−Z Hi−Z D[15:8] DB[7:0] D[7:0] Hi−Z Hi−Z D[7:0] †Signal internal to device Figure 1.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 tw1 tw2 CONVST tpd1 tw4 tpd2 tw3 BUSY tw7 tsu6 tsu6 CS tpd3 CONVERT† tCONV tCONV tHOLD SAMPLING† (When CS Toggle) tACQ tsu(AB) tsu(AB) tsu5 BYTE tsu5 th1 tsu5 tsu5 tdis tsu2 tpd4 th2 ten RD = 0 ten ten DB[15:8] Hi−Z Previous D [15:8] tdis Hi−Z D[15:8] DB[7:0] Previous Hi−Z D [7:0] Hi−Z Hi−Z Previous D [15:8] Hi−Z Previous D [7:0] D[7:0] D[7:0] †Signal internal to device Figure 2.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 tpd3 CONVERT† tCONV tCONV tHOLD t(ACQ) SAMPLING† (When CS = 0) tsu(AB) tsu(AB) tsu5 BYTE tsu5 th1 tpd4 th2 RD tdis ten DB[15:8] Hi−Z Hi−Z D[15:8] DB[7:0] Hi−Z D[7:0] Hi−Z D[7:0] †Signal internal to device Figure 3.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT† tCONV tCONV tpd3 tpd3 tHOLD tHOLD t(ACQ) SAMPLING† (When CS = 0) tsu(AB) tsu(AB) BYTE tsu5 tsu5 th1 th1 tdis tsu5 tsu5 RD = 0 td5 DB[15:8] Previous D[7:0] D[7:0] Next D[15:8] D[15:8] DB[7:0] Next D[7:0] D[7:0] †Signal internal to device Figure 4.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS(1) HISTOGRAM (DC CODE SPREAD) HALF SCALE 4096 CONVERSIONS 2000 1800 1600 +VA = 5 V, +VBD = 5 V, TA = 255C, fs = 750 KSPS 1400 Count 1200 1000 800 600 400 200 32766 32765 32764 32763 32762 32761 32760 32759 32758 32757 0 code Figure 6 GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.1 0.1 +VA = 5 V, +VBD = 5 V, fs = 750 KSPS, Vref = 4.096 V E G − Gain Error − %FS 0.06 0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 OFFSET ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs FREE-AIR TEMPERATURE 1 1 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 4.096 V 0.8 0.6 0.4 EO − Offset Error − mV EO − Offset Error − mV 0.6 0.2 0.0 −0.2 −0.4 0.4 0.2 0 −0.2 −0.4 −0.6 −0.6 −0.8 −0.8 −1 −40 −15 10 35 60 TA − Free-Air Temperature − °C +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 2.5 V 0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 INTEGRAL NONLINEARITY vs SAMPLE RATE DIFFERENTIAL NONLINEARITY vs SAMPLE RATE 0.5 DNL − Differential Nonlinearity − LSBs 0.8 INL − Integral Nonlinearity − LSBs MAX 0.6 0.4 +VA = 5 V, +VBD = 5 V, TA = 255C, Vref = 4.096 V 0.2 0 −0.2 −0.4 −0.6 MIN −0.8 −1 125 250 375 500 Sample Rate − KSPS 625 0.2 0.1 0 −0.1 −0.2 MIN −0.3 −0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SUPPLY CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 0.6 25.6 I DD − Supply Current − mA 25.4 25.2 DNL − Differential Nonlinearity − LSBs TA = 255C, fS = 750 KSPS, Vref = 4.096 V 25 24.8 24.6 24.4 24.2 24 23.8 23.6 4.75 5 VDD − Supply Voltage − V MAX 0.4 0.2 0 −0.2 MIN −0.4 −0.6 4.75 5.25 Figure 17 0.8 DNL − Differential Nonlinearity − LSBs INL − Integral Nonlinearity − LSBs MAX 0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 OFFSET ERROR vs REFERENCE VOLTAGE 0.8 0.5 0.6 0.4 MAX 0.4 0.3 +VBD = 5 V, +VA = 5 V, TA = 255C, fS = 750 KSPS 0.2 0 EO − Offset Error − mV INL − Integral Nonlinearity − LSBs INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE −0.2 −0.4 −0.6 MIN 0.2 0.1 0 −0.1 −0.2 −0.8 −0.3 −1 −0.4 −1.2 2.5 2.84 3.18 3.52 3.86 Vref − Reference Voltage − V +VBD = 5 V, +VA = 5 V, TA = 255C, fS = 750 KSPS −0.5 2.5 4.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 90 110 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 105 100 SINAD − Signal-to-Noise and Distortion − dB SFDR − Spurious Free Dynamic Range − dB SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 95 90 85 80 75 −15 10 35 60 88 87 86 85 84 83 82 81 80 −40 70 −40 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY 90 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V −85 SINAD − Signal-to-Noise and Distortion − dB THD − Total Harmonic Distortion − dB −80 −90 −95 −100 −105 −110 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 +VA SUPPLY CURRENT vs SAMPLE RATE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 26 25.8 +VA = 5.25 V, +VBD = 5.25 V, fS = 750 KSPS, Vref = 4.096 V +VA − Supply Current − mA 25.6 25.5 25.4 25.3 25.2 25 +VA = 5.25 V, +VBD = 5.25 V, TA = 255C, Vref = 4.096 V 24.5 24 23.5 23 22.5 22 25.1 −40 −15 10 35 60 85 21.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 DIFFERENTIAL NONLINEARITY 3 +VA = 5 V, +VBD = 5 V, TA = 255C, fS = 750 KSPS, Vref = 4.096 V DNL − LSBs 2 1 0 −1 −2 −3 0 16384 32768 49152 65536 Code Figure 36 FFT 0 −20 +VA = 5 V, +VBD = 3 V, TA = 255C, fS = 750 KSPS, fi = 99 kHz, VI = 4 Vpp, 16384 Points,Vref = 4.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8371 to 8-Bit Microcontroller Interface Figure 38 shows a parallel interface between the ADS8371 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V REF 3040 0.1 µF OUT AGND 10 µF Ext Ref Input 100 Ω 0.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 PRINCIPLES OF OPERATION The ADS8371 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 38 for the application circuit for the ADS8371. The conversion clock is generated internally. The conversion time of 1.13 µs is capable of sustaining a 750-kHz throughput.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 ADS8371 + _ Unipolar Input THS4031 _ + 15 Ω +IN 200 pF −IN 50 Ω Figure 39. Unipolar Input to Converter In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8371 within its rated operating voltage range.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 Digital Inputs The converter switches from sample to hold mode at the falling edge of the CONVST input pin. A clean and low jitter falling edge is important to the performance of the converter. A sharp falling transition on this pin can affect the voltage that is acquired by the converter. A falling transition time in the range of 10 ns to 30 ns is required to achieve the rated performance of the converter.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 A similar precaution applies when RD is used to three-state the output buffers after a data-read operation. A minimum quite period of 125 ns is also required from the instant the data is changed on the bus (such as the falling or rising edge of RD, the falling or rising edge of BYTE, and the falling is made available on the data bus pins to the sampling instant (falling edge of CONVST).
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 Reading Data The ADS8371 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1.
www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8371 circuitry. As the ADS8371 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8371IBPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS8371IBPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS8371IPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8371IBPFBR TQFP PFB 48 1000 367.0 367.0 38.0 ADS8371IBPFBT TQFP PFB 48 250 367.0 367.0 38.0 ADS8371IPFBT TQFP PFB 48 250 367.0 367.0 38.
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
