Datasheet

3-2
Table 3−2.Jumper Settings
Jumper Settings
Reference Designator Description
1−2 2−3
Connect +5 VD from connector to +BVDD Installed
†
W1
Connect +3.3 VD from connector to +BVDD
Set A[2..0] = 0x1 to generate RD pulse Installed
†
W2
Set A[2..0] = 0x2 to generate RD pulse
Set A[2..0] = 0x3 to generate convst pulse Installed
†
W3
Set A[2..0] = 0x4 to generate convst pulse
Set inverted BUSY pulse
W4
Set BUSY pulse to INTC# Installed
†
†
Factory-set condition
The data bus is available at connector P3; see Table 3−3 for pinout
information.
Table 3−3.Data Bus Connector P3
Connector.Pin Signal Description
P3.1 D0 Buffered Data Bit 0 (LSB)
P3.3 D1 Buffered Data Bit 1
P3.5 D2 Buffered Data Bit 2
P3.7 D3 Buffered Data Bit 3
P3.9 D4 Buffered Data Bit 4
P3.11 D5 Buffered Data Bit 5
P3.13 D6 Buffered Data Bit 6
P3.15 D7 Buffered Data Bit 7
P3.17 D8 Buffered Data Bit 8
P3.19 D9 Buffered Data Bit 9
P3.21 D10 Buffered Data Bit 10
P3.23 D11 Buffered Data Bit 11
P3.25 D12 Buffered Data Bit 12
P3.27 D13 Buffered Data Bit 13
P3.29 D14 Buffered Data Bit 14
P3.31 D15 Buffered Data Bit 15 (MSB)
Note: All even-numbered pins of P3 are tied to DGND.
This evaluation module provides direct access to all the analog-to-digital
converter control signals via connector J2; see Table 3−4.
Table 3−4.Pinout for Converter Control Connector, J2
Connector.Pin Signal Description
J2.1 CS Chip Select pin. Active low
J2.3 RD Read pin. Active low
J2.5 CONVST Convert start pin. Active low
J2.7 BYTE Byte select input. Used for 8-bit bus reading.
J2.9 N/C Not Connected
J2.11 BUSY Converter status output. High when a conversion is in progress.
Note: All even-numbered pins of J2 are tied to DGND.