Datasheet
RESET
EOC
RD
Register5
Register4
empty
empty
empty
empty
empty
empty
empty
empty
empty
empty
CH A1
CH A0
empty
empty
empty
empty
empty
CH A1
empty
CH C1
CH C0
CH B1
CH B0
CH A1
empty
empty
CH C1
CH C0
CH B1
CH B0
CH C1
CH C0
CH C1
CH C0
CH B1
CH B0
Conversion
Channel A
Conversion
ChannelC
Conversion
ChannelsBandC
t
0
t
2
t
3
t
4
t
5
t
6
Register3
Register2
Register1
Register0
t
1
The Output Code (DB15 … DB0)
ADS8365
SBAS362C – AUGUST 2006 – REVISED MARCH 2008 ....................................................................................................................................................
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Figure 31. Functionality Diagram of the FIFO Registers
On t
5
, the new read process of channel A1 data is second RD, the 16-bit data word can be read
finished. The new data of channel C0 and C1 at t
6
(DB15 … DB0). If BYTE = 1, then three RD impulses
are put on top (registers 4 and 5). are needed. On the first RD impulse, data valid, the
three address bits, and data bits DB3 … DB0 (DV, A2,
In Cycle mode and in FIFO mode, the ADS8365
A1, A0, DB3, DB2, DB1, DB0) are read, followed by
offers the ability to add the address of the channel to
the eight lower bits of the 16-bit data word
the output data. Since there is only a 16-bit bus
(db7 … db0), and finally the higher eight data bits
available (or 8-bit bus in the case BYTE is high), an
(DB15 … DB8). 1000 0000 0000 is added before the
additional RD signal is necessary to get the
address in case BYTE = 0, and DB3 … DB0 is added
information (see Table 2 and Table 3 ).
after the address if BYTE = 1. This provides the
possibility to check if the counting of the RD signals
In FIFO mode, a dummy read signal ( RD) is required
inside the ADS8365 are still tracking with the external
after a reset signal to set the address bits
interface (see Table 2 and Table 3 ).
appropriately; otherwise, the first conversion will not
be valid. This is only necessary in FIFO mode.
The data valid bit is useful for the FIFO mode. Valid
data can simply be read until the data valid bit equals
0. The three address bits are listed in Table 5 . If the
FIFO is empty, 16 zeroes are loaded to the output.
In the standard address mode (A2 A1 A0 =
000 … 101), the ADS8365 has a 16-bit output word on
Table 5. Address Bit in the Output Data
pins DB15 … DB0, if BYTE = 0. If BYTE = 1, then two
RD impulses are necessary to first read the lower
DATA FROM ... A2 A1 A0
bits, and then the higher bits on either DB7 … DB0 or
Channel A0 0 0 0
DB15...DB8.
Channel A1 0 0 1
If the ADS8365 operates in Cycle or in FIFO mode
Channel B0 0 1 0
and ADD is set high, then the address of the channel
Channel B1 0 1 1
(A2A1A0) and a data valid (DV) bit are added to the
Channel C0 1 0 0
data. If BYTE = 0, then the data valid and the
Channel C1 1 0 1
address of the channel is active during the first RD
impulse (1000 0000 0000 DV A2 A1 A0). During the
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